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general description the DS1878 controls and monitors all functions for sff,sfp, and sfp+ modules including all sff-8472 func- tionality. the combination of the DS1878 with maxim laser driver/limiting amplifier solutions supports vcsel, dfb, and eml-based solutions. the device provides apc loop, modulation current control, and eye safety functionality. it continuously monitors for high output current, high bias current, and low and high transmit power to ensure that laser shutdown for eye safety requirements are met without adding external compo- nents. six adc channels monitor v cc , temperature, and four external monitor inputs (mon1?on4) thatcan be used to meet all monitoring requirements. mon3 is differential with support for common mode to v cc . two digital-to-analog (dac) outputs with tempera- ture-indexed lookup tables (luts) are available foradditional control functionality. applications sff, sfp, and sfp+ transceiver modules features ? meets all sff-8472 control and monitoringrequirements ? laser bias controlled by apc loop andtemperature lut to compensate for tracking error ? laser modulation controlled by temperature lut ? six analog monitor channels: temperature, v cc , mon1?on4 mon1?on4 support internal and external calibration scalable dynamic rangeinternal direct-to-digital temperature sensor alarm and warning flags for all monitored channels ? two 9-bit delta-sigma outputs with 36 entrytemperature luts ? digital i/o pins: five inputs, four outputs ? comprehensive fault-measurement system withmaskable laser shutdown capability ? flexible, two-level password scheme providesthree levels of security ? 256 additional bytes located at a0h slaveaddress ? i 2 c-compatible interface ? 3-wire master to communicate with a maximlaser driver/limiting amplifier ? +2.85v to +5.5v operating voltage range ? -40? to +95? operating temperature range ? 28-pin tqfn (5mm x 5mm x 0.75mm) package DS1878 ________________________________________________________________ maxim integrated products 1 ordering information 19-5537; rev 1; 8/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. t&r = tape and reel. * ep = exposed pad. part temp range pin-package DS1878t+ -40c to +95c 28 tqfn-ep* DS1878t+t&r -40c to +95c 28 tqfn-ep* sfp+ controller with digital ldd interface downloaded from: http:///
DS1878 2 _______________________________________________________________________________________ absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 dac1, dac2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 analog input characteristics (mon2, txp hi, txp lo, hbias, los) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 analog voltage monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 digital thermometer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 control loop and quick-trip timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3-wire digital interface specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 i 2 c ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 nonvolatile memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 typical operating circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3-wire dac control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 bias register/apc control, 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 modulation control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 bias and modulation control during power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 bias and modulation registers as a function of transmit disable (txd) . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 apc and quick-trip timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 monitors and fault detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 five quick-trip monitors and alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 six adc monitors and alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 adc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 right-shifting adc result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 enhanced rssi monitoring (dual-range functionality) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 low-voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 power-on analog (poa) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 delta-sigma outputs (dac1 and dac2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 digital i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 los, losout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 in1, rsel, rselout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 txd, txdout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 table of contents sfp+ controller with digital ldd interface downloaded from: http:///
DS1878 transmit fault (txfout) output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 die identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 3-wire master for controlling the maxim laser driver and limiting amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 3-wire interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 DS1878 master communication interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 manual operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 slave register map and DS1878 corresponding location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 i 2 c communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 i 2 c definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 i 2 c protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 shadowed eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 lower memory register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 01h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 02h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 04h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 05h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 06h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 table 07h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 table 08h register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 auxiliary a0h memory register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 lower memory register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 01h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 table 02h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 table 04h register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 table 06h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 table 07h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 table 08h register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 auxiliary memory a0h register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 power-supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 sda and scl pullup resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 table of contents (continued) sfp+ controller with digital ldd interface downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 4 _______________________________________________________________________________________ figure 1. modulation lut loading to a maxim laser driver mod dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 2. power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 3. txd timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 4. apc loop and quick-trip sample timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 5. adc round-robin timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 6. mon2 v cc or gnd reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 7. mon3 differential input for high-side rssi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 figure 8. rssi with crossover enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 figure 9. rssi with crossover disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 10. low-voltage hysteresis example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 figure 11. recommended rc filter for dac1/dac2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 12. delta-sigma outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 13. dac1/dac2 lut assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 figure 14. 3-wire communication on rselout transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 15. logic diagram 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 16. logic diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 17a. txfout nonlatched operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 17b. txfout latched operation and txd_txfen = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 17c. txfout when txd_txfen = 0 on fast power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 figure 17d. txfout when txd_txfen = 0 on slow power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 18. 3-wire timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 19. 3-wire state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 figure 20. i 2 c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 21. example i 2 c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 22. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 1. acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 2. update rate timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 3. adc default monitor full-scale ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 4. mon3 hysteresis threshold values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 5. mon3 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 list of figures list of tables downloaded from: http:///
DS1878 stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on mon1?on4, rsel, csel1out, csel2out, sclout, sdaout, txdout, in1,los, txf, txfout, and txd pins relative to ground .................................-0.5v to (v cc + 0.5v)* voltage range on v cc , sda, scl, rselout, and losout pins relative to ground ..................-0.5v to +6v continuous power dissipation (t a = +70?) 28 pin tqfn (derate 34.5mw/? above +70?) .....2758.6mw operating temperature range ...........................-40? to +95? programming temperature range .........................0? to +95? storage temperature range .............................-55? to +125? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units main supply voltage v cc (note 1) 2.85 5.5 v high-level input voltage (sda, scl, sdaout) v ih:1 0.7 x v cc v cc + 0.3 v low-level input voltage (sda, scl, sdaout) v il:1 -0.3 0.3 x v cc v high-level input voltage (txd, txf, rsel, in1, los) v ih:2 2.0 v cc + 0.3 v low-level input voltage (txd, txf, rsel, in1, los) v il:2 -0.3 +0.8 v dc electrical characteristics(v cc = +2.85v to +5.5v, t a = -40? to +95?, unless otherwise noted.) * subject to not exceeding +6v. recommended operating conditions(t a = -40? to +95?, unless otherwise noted.) absolute maximum ratings sfp+ controller with digital ldd interface _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units supply current i cc (notes 1, 2) 2.5 4 ma output leakage (sda, sdaout, rselout, losout, txfout) i lo 1 a i ol = 4ma 0.4 low-level output voltage (sda, sdaout, sclout, csel1out, csel2out, rselout, losout, txdout, dac1, dac2, txfout) v ol i ol = 6ma 0.6 v high-level output voltage (dac1, dac2, sclout, sdaout, csel1out, csel2out, txdout) v oh i oh = 4ma v cc - 0.4 v txdout before eeprom recall dac1 and dac2 before recall high impedance before recall 55 550 100 m input leakage current (in1, los, rsel, scl, txd, txf) i li 1 a digital power-on reset pod 1.0 2.2 v analog power-on reset poa 2.0 2.75 v downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 6 _______________________________________________________________________________________ parameter symbol conditions min typ max units adc resolution 13 bits input/supply accuracy (mon1Cmon4, v cc ) acc at factory setting 0.25 0.5 %fs sample rate for temperature, mon1Cmon4, and v cc t rr 64 75 ms input/supply offset (mon1Cmon4, v cc ) v os (note 5) 0 5 lsb mon1Cmon4 2.5 v cc 6.5536 v factory setting full-scale (note 6) mon3 fine 312.5 v analog voltage monitoring characteristics(v cc = +2.85v to +5.5v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units mon2, txp hi, txp lo, hbias, los full-scale voltage (note 3) 1.25 v mon2 input resistance 35 50 65 k resolution (note 3) 8 bits error t a = +25c (note 4) 2 %fs integral nonlinearity -1 +1 lsb differential nonlinearity -1 +1 lsb temperature drift -2.5 +2.5 %fs analog input characteristics (mon2, txp hi, txp lo, hbias, los)(v cc = +2.85v to +5.5v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units main oscillator freq uency f osc 5 mhz delta-sigma input-clock frequency f ds 1.25 mhz reference voltage input (refin) v refin minimum 0.1f to gnd 2 v cc v output range 0 v refin v output resolution see the delta-sigma outputs (dac1 and dac2) section for details 9 bits output impedance r ds 35 100 dac1, dac2 electrical characteristics(v cc = +2.85v to +5.5v, t a = -40? to +95?, unless otherwise noted.) downloaded from: http:///
DS1878 parameter symbol conditions min typ max units sclout clock frequency f sclout 833 khz sclout duty cycle t 3wdc 50 % sdaout setup time t ds 100 ns sdaout hold time t dh 100 ns csel1out, csel2out pulse- width low t csw 500 ns csel1out, csel2out leading time before the first sclout edge t l 500 ns csel1out, csel2out trailing time after the last sclout edge t t 500 ns sdaout, sclout load c b3w total bus capacitance on one line 10 pf parameter symbol conditions min typ max units output-enable time following poa t init (note 7) 20 ms binary search time t search (note 11) 8 10 bias samples 3-wire digital interface specification (v cc = +2.85v to +5.5v, t a = -40? to +95?, timing referenced to v il(max) and v ih(min) , unless otherwise noted.) (figure 17) sfp+ controller with digital ldd interface _______________________________________________________________________________________ 7 parameter symbol conditions min typ max units txd enable t off from rising txd to rising txdout 5 s recovery from txd disable t on from falling txd to falling txdout 5 s t initr1 from falling txd 131 fault reset time (to txfout = 0) t initr2 on power-up or falling txd, when vcc lo alarm is detected (note 7) 161 ms fault assert time (to txfout = 1) t fault after htxp, ltxp, hbath, ibiasmax (note 8) 6.4 55 s losout assert time t loss_on llos (notes 8, 9) 6.4 55 s losout deassert time t loss_off hlos (notes 8, 10) 6.4 55 s control loop and quick-trip timing characteristics(v cc = +2.85v to +5.5v, t a = -40? to +95?, unless otherwise noted.) ac electrical characteristics(v cc = +2.85v to +5.5v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units thermometer error t err -40c to +95c -3 +3 c digital thermometer characteristics(v cc = +2.85v to +5.5v, t a = -40? to +95?, unless otherwise noted.) downloaded from: http:///
note 1: all voltages are referenced to ground. current into the ic is positive, and current out of the ic is negative. note 2: inputs are at supply rail. outputs are not loaded. note 3: eight ranges allow the full-scale range to change from 312mv to 1.25v. note 4: the output impedance of the device is proportional to its scale setting. for instance, if using the 1/2 scale, the outputimpedance is 1.5k . note 5: this parameter is guaranteed by design. note 6: full-scale is programmable. note 7: a temperature conversion is completed and the modulation register value is recalled from the lut and v cc has been measured to be above the vcc lo alarm. note 8: the timing is determined by the choice of the sample rate setting (see table 02h, register 88h). note 9: this specification is the time it takes from mon3 voltage falling below the llos trip threshold to losout asserted high. note 10: this specification is the time it takes from mon3 voltage rising above the hlos trip threshold to losout asserted low. note 11: assuming an appropriate initial step is programmed that would cause the power to exceed the apc set point within foursteps, the bias current will be within 3% within the time specified by the binary search time. see the bias and modula- tion control during power-up section. note 12: i 2 c interface timing shown is for fast-mode (400khz) operation. this device is also backward compatible with i 2 c stan- dard-mode timing. note 13: c b ?he total capacitance of one bus line in pf. note 14: eeprom write begins after a stop condition occurs. parameter symbol conditions min typ max units scl clock frequency f scl (note 12) 0 400 khz clock pulse-width low t low 1.3 s clock pulse-width high t high 0.6 s bus-free time between stop and start condition t buf 1.3 s start hold time t hd:sta 0.6 s start setup time t su:sta 0.6 s data in hold time t hd:dat 0 0.9 s data in setup time t su:dat 100 ns rise time of both sda and scl signals t r (note 13) 20 + 0.1c b 300 ns fall time of both sda and scl signals t f (note 13) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 s capacitive load for each bus line c b 400 pf eeprom write time t wr (note 14) 20 ms DS1878 sfp+ controller with digital ldd interface 8 _______________________________________________________________________________________ nonvolatile memory characteristics(v cc = +2.85v to +5.5v, unless otherwise noted.) parameter symbol conditions min typ max units at +25c 200,000 eeprom write cycles at +85c 50,000 i 2 c ac electrical characteristics (v cc = +2.85v to +5.5v, t a = -40? to +95?, timing referenced to v il(max) and v ih(min) , unless otherwise noted.) (figure 19) downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface _______________________________________________________________________________________ 9 typical operating characteristics (v cc = +2.85v to +3.9v, t a = +25?, unless otherwise noted.) supply current vs. supply voltage DS1878 toc01 v cc (v) supply current (ma) 3.85 3.60 3.10 3.35 1.7 1.9 2.1 2.3 2.7 2.5 2.9 1.5 2.85 +95 c sda = scl = v cc -40 c +25 c supply current vs. temperature DS1878 toc02 temperature ( c) supply current (ma) 80 60 40 20 0 -20 2.1 2.2 2.3 2.4 2.5 2.6 2.72.0 -40 v cc = 3.3v v cc = 3.9v v cc = 2.85v sda = scl = v cc mon1?mon4 inl DS1878 toc03 mon1?mon4 input voltage (v) mon1?mon4 inl (lsb) 2.0 1.5 1.0 0.5 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 2.5 v cc = 3.3v using factory-programmed full-scalevalue of 2.5v mon1?mon4 dnl DS1878 toc04 mon1?mon4 input voltage (v) mon1?mon4 dnl (lsb) 2.0 1.5 1.0 0.5 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 2.5 v cc = 3.3v using factory-programmed full-scalevalue of 2.5v dac1 and dac2 dnl DS1878 toc05 dac1 and dac2 position (dec) dac1 and dac2 dnl (lsb) 500 400 300 200 100 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 dac1 and dac2 inl DS1878 toc06 dac1 and dac2 position (dec) dac1 and dac2 inl (lsb) 500 400 100 200 300 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 0 downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 10 ______________________________________________________________________________________ pin description pin configuration pin name function 1 rselout rate-select output 2 scl i 2 c serial-clock input 3 sda i 2 c serial-data input/output 4 txfout transmit fault output, open drain 5 los loss of signal input 6 in1 digital input. general-purpose input, as1 in sff-8079, or rs1 in sff-8431. 7 txd transmit disable input 8, 17, 21 gnd ground connection 9 rsel rate-select input 10 txdout transmit disable output 11 mon4 external monitor input 4 12, 13 mon3p, mon3n differential external monitor input 3 and los quick trip 14 mon1 external monitor input 1 and hbath quick trip 15, 23 v cc power-supply input 16 mon2 external monitor input 2, feedback voltage for apc loop, and txp hi/txp lo quick trip pin name function 18 refin reference input for dac1 and 19 dac1 delta-sigma output 1 20 dac2 delta-sigma output 2 22 csel2out chip-select output 2. part of 3-wire interface to a laser driver/limiting amplifier. 24 csel1out chip-select output 1. part of 3-wire interface to a laser driver/limiting amplifier. 25 sclout serial-clock output. part of 3-wire interface to a laser driver/limiting amplifier. 26 sdaout serial-data input/output. part of 3-wire interface to a laser driver/limiting amplifier. 27 losout receive loss-of-signal output 28 txf transmit fault input ep exposed pad. connect to ground. thin qfn (5mm 5mm 0.75mm) top view 2627 25 24 10 9 11 scl txfout los in1 txd 12 rselout dac2refin gnd gndmon2 v cc 12 sclout 4567 20 21 19 17 16 15 sdaout losout mon3pmon4 txdout rsel sda dac1 3 18 28 8 txf gnd csel1out 23 13 mon3n v cc 22 14 mon1 csel2out DS1878 ep + downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 11 block diagram analog mux main memory eeprom/sram adc configuration/results, system status/control bits, alarms/warnings, lookup tables, user memory i 2 c interface 3-wire interface temperature sensor configurable logic power-on analog interrupt eeprom 256 bytes at a0h sda scl v cc v cc v cc mon1 mon2 mon4 mon3p mon3n configurable logic 9-bit delta-sigma 9-bit delta-sigma apc integrator 13-bit adc 8-bit qts dac1 dac2 sdaout sclout csel1out csel2outtxfout refintxdout rseloutlosout txd txf rsel in1 los gnd DS1878 v cc v cc downloaded from: http:///
los txf txdout txd fault disable rsel rselout los losout txfout tx_fault sda scl mode_def2 (sda)rate select los mode_def1 (scl) tx_disable mode dac bias dac ldd eeprom quick trip los adc i 2 c 3w 3w cs1 DS1878 max3946 3w cs2 max3945 mon1 mon2mon3 bmon r mon 680 +3.3v r bd la pin-rosa dfb tosa DS1878 sfp+ controller with digital ldd interface 12 ______________________________________________________________________________________ detailed description the DS1878 integrates the control and monitoring func-tionality required to implement a vcsel-based or dfb- based sfp or sfp+ system using maxim? limiting amplifiers and laser drivers. key components of the device are shown in the block diagram and described in subsequent sections. 3-wire dac control the device controls two 9-bit dacs inside the maximlaser drivers. one dac is used for laser bias control, while the other is used for modulation amplitude control. the device communicates with the laser driver over a 3- wire digital interface (see the 3-wire master for controlling the maxim laser driver section). the com- munication between the device and maxim laser driverand/or limiting amplifier is transparent to the end user. typical operating circuit downloaded from: http:///
bias register/apc control, 3-wire mode a maxim laser driver controls its laser bias current dacusing the apc loop within the device. the apc loop? feedback to the device is the monitor diode (mon2) current, which is converted to a voltage using an exter- nal resistor. the feedback is sampled by a comparator and compared to a digital set-point value. the output of the comparator has three states: up, down, or no-oper- ation. the no-operation state prevents the output from excessive toggling once steady state is reached. as long as the comparator output is in either the up or down states, the bias is adjusted by writing increment and decrement values to the maxim laser driver through the biasinc register. the device has an lut to allow the apc set point to change as a function of temperature to compensate for tracking error (te). the apc lut has 36 entries that determine the apc setting in 4? windows between -40? and +100?. modulation control a maxim laser driver controls the laser modulationusing the internal temperature-indexed lut within the device. the modulation lut is programmed in 2? increments over the -40? to +102? range to provide temperature compensation for the laser? modulation. the modulation is updated after each temperature con- version using the 3-wire interface that connects to the maxim laser driver. a maxim laser driver include a 9-bit dac. the modulation lut is 8 bits. figure 1 demonstrates how the 8-bit lut controls the 9-bit dac with the use of a temperature control bit DS1878 ______________________________________________________________________________________ 13 table 1. acronyms acronym definition adc analog-to-digital converter agc automatic gain control apc automatic power control apd avalanche photodiode atb alarm trap bytes bm burst mode dac digital-to-analog converter dfb distributed feedback laser ldd laser diode driver los loss of signal lut lookup table nv nonvolatile qt quick trip te tracking error tia transimpedance amplifier rosa receiver optical subassembly see shadowed eeprom sff small form factor sff-8472 document defining register map of sfps and sffs sfp small form factor pluggable sfp+ enhanced sfp tosa transmit optical subassembly txp transmit power vcsel vertical cavity self-emitting laser sfp+ controller with digital ldd interface mod lut loaded to [7:0] mod lut loaded to [7:0] modti 8 7 6 5 4 3 2 10 modti modtc = 0 temperature ( c) -40 +102 temperature ( c) -40 +102 modtc = 1 mod lut loaded to [8:1] (dac bit 0 = 0) mod lut loaded to [8:1] (dac bit 0 = 0) max3798 dac bit 8 7 6 5 4 3 2 10 max3798 dac bit figure 1. modulation lut loading to a maxim laser driver mod dac downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 14 ______________________________________________________________________________________ (modtc, table 02h, register c6h) and a temperatureindex register (modti, table 02h, register c2h). bias and modulation control during power-up the device has two internal registers, modulation and bias, that represent the values written to the maximlaser driver? modulation dac and bias dac through the 3-wire interface. on power-up, the device sets the modulation and bias registers to 0. when v cc is above poa, the device initializes the maxim laser driver. after a temperature conversion is completed and if thevcc lo alarm is enabled, an additional v cc conversion above the customer-defined vcc lo alarm level isrequired before a maxim laser driver modulation register is updated with the value determined by the temperature conversion and the modulation lut. when the modulation register is set, the bias regis- ter is set to a value equal to istep (see figure 2). the startup algorithm verifies whether this bias current caus- es a feedback voltage above the apc set point, and if not, it continues increasing the bias register by istep until the apc set point is exceeded. when the apc set point is exceeded, the device begins a binary search to quickly reach the bias current corresponding to the proper power level. after the binary search is complet- ed, the apc integrator is enabled and single lsb steps are used to tightly control the average power. the txp hi, txp lo, and bias max qt alarms aremasked until the binary search is completed. however, the bias max alarm is monitored during this time to prevent the bias register from exceeding ibiasmax. during the bias current initialization, the bias register is not allowed to exceed ibiasmax. if this occurs during the istep sequence, then the binary search routine is enabled. if ibiasmax is exceeded during the binary search, the next smaller step is acti- vated. istep or binary increments that would cause the bias register to exceed ibiasmax are not taken. masking the alarms until the completion of the binary search prevents false positive alarms during startup. istep is a value controlled by registers isteph, istepl, and istepti (table 02h, registers bah, bbh, and c5h, respectively). see the register descriptions for more information. during the first steps, a maxim laser driver? bias dac is directly written using set_ibias. istep should be programmed to the maximum safe increase that is allowable during startup. if this value is programmed too low, the device still operates, but it could take significantly longer for the algorithm to con- verge and hence to control the average power. if a fault is detected, and txd is toggled to reenable the outputs, the device powers up following a similar sequence to an initial power-up. the only difference is that the device already has determined the present 1234567891 01 11 21 3 v poa modulation register bias register v cc bias sample t init t search binary search apc integrator on 4x istep 3x istep 2x istep istep figure 2. power-up timing downloaded from: http:///
temperature, so the t init time is not required for the device to recall the apc and mod set points from eeprom. bias and modulation registers as a function of transmit disable (txd) if txd is asserted (logic 1) during normal operation,the 3-wire master writes the laser driver bias and modulation dacs to 0. when txd is deasserted (logic 0), the device sets the modulation register with the value associated with the present temperature, and initializes the bias register using the same search algorithm as done at startup. when asserted, soft txd (txdc) (lower memory, register 6eh) would allow a software control identical to the txd pin (see figure 3). apc and quick-trip timing as shown in figure 4, the device? input comparator isshared between the apc control loop and the quick- trip alarms (txp hi, txp lo, los, bias hi, and ibias max). the comparator polls the alarms in a multiplexed sequence. five of every eight comparator readings are used for apc loop bias-current control. the other three updates are used to check the htxp/ltxp (monitor diode voltage), the hbath (mon1), and los (mon3) signals against the internal apc, bias, and mon3 ref- erence, respectively. if the last apc comparison was higher than the apc set point, it makes an htxp com- parison, and if it is lower, it makes an ltxp compari- son. depending on the results of the comparison, the corresponding alarms and warnings (txp hi, txp lo) are asserted or deasserted. the device has a programmable comparator sampletime based on an internally generated clock to facilitate a wide variety of external filtering options and time delays resulting from writing values to the laser driver? bias dac. the sample rate register (table 02h, register 88h) determines the sampling time. samples occur at a regular interval, t rep . table 2 shows the sample rate options available. any quick-trip alarm thatis detected by default remains active until a subse- quent comparator sample shows the condition no longer exists. a second bias current monitor (bias max) compares a maxim laser driver? bias dac? code to a digital value stored in the ibiasmax register. this comparison is made at every bias current update to ensure that a high-bias current is quickly detected. DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 15 apc quick-trip sample times hbias sample hbias sample los sample apc sample apc sample apc sample apc sample apc sample apc sample htxp/ltxp sample t rep figure 4. apc loop and quick-trip sample timing table 2. update rate timing apc_sr[2:0] sample period (t rep ) (ns) 000b 800 001b 1200 010b 1600 011b 2000 100b 2800 101b 3200 110b 4400 111b 6400 t off t on txd txdout figure 3. txd timing downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 16 ______________________________________________________________________________________ an apc sample that requires an update of the biasregister causes subsequent apc samples to be ignored until the end of the 3-wire communication that updates the laser driver? bias dac, plus an additional 16 sample periods (t rep ). monitors and fault detection monitors monitoring functions on the device include five quick-trip comparators and six adc channels. this monitoringcombined with the alarm enables (table 01h/05h) deter- mines when/if the device turns off the maxim laser dri- ver? dacs and triggers the txfout and txdoutoutputs. all the monitoring levels and interrupt masks are user programmable. five quick-trip monitors and alarms five quick trip monitors are provided to detect potentiallaser safety issues and los status. these monitor the following: 1) high bias current (hbath), causing qt bias hi 2) low transmit power (ltxp), causing qt txp lo 3) high transmit power (htxp), causing qt txp hi 4) max output current (ibiasmax), causing qt bias max 5) loss of signal (llos), causing qt los lo the high and low transmit power quick-trip registers (htxp and ltxp) set the thresholds used to compare against the mon2 voltage to determine if the transmit power is within specification. the hbath quick trip compares the mon1 input (generally from a maxim laser driver bias monitor output) against its threshold setting to determine if the present bias current is above specification. the user can program up to eight differ- ent temperature-indexed threshold levels for hbath (table 02h, registers d0h?7h). the bias max quick trip compares the bias register with the mon2 voltage and determines if the bias reg- ister is above specification. the bias register is not allowed to exceed the value set in the ibiasmax regis- ter. when the device detects the bias is at the limit, it sets the bias max status bit and holds the bias regis- ter setting at the ibiasmax level. the los lo quick trip compares the mon3 inputagainst its threshold setting (llos) to determine if the present received power is below the specification. the los ranging register allows the los threshold value to scale. the los lo quick trip can be used to set the losout pin. los hi does not set losout. see the description of the los lo and los hi bits (table 01h, register fbh) for further details of operation. the quick trips are routed to create txfout through interrupt masks to allow combinations of these alarms to be used to trigger the outputs. six adc monitors and alarms the adc monitors six channels that measure tempera-ture (internal temp sensor), v cc , and mon1?on4 using an analog multiplexer to measure them roundrobin with a single adc (see the adc timing section). the five voltage channels have a customer-programma-ble full-scale range and all channels have a customer- programmable offset value that is factory programmed to default value (see table 3). additionally, mon1?on4 can right-shift results by up to 7 bits before the results are compared to alarm thresholds or read over the i 2 c bus. this allows customers with specified adc ranges tocalibrate the adc full scale to a factor of 1/2 n of their specified range to measure small signals. the device can then right-shift the results by n bits to maintain the bitweight of their specification (see the right-shifting adc result and enhanced rssi monitoring (dual-range functionality) sections). the adc results (after right-shifting, if used) are com-pared to the alarm and warning thresholds after each conversion, and the corresponding alarms are set, which can be used to trigger the txfout output. these adc thresholds are user programmable, as are the masking registers that can be used to prevent the alarms from triggering the txfout output. adc timing there are six analog channels that are digitized in around-robin fashion in the order shown in figure 5. the total time required to convert all six channels is t rr (see the analog voltage monitoring characteristics for details). table 3. adc default monitor full-scale ranges signal (units) +fs signal +fs hex -fs signal -fs hex temperature (c) 127.996 7fff -128 8000 v cc (v) 6.5528 fff8 0 0000 mon1Cmon4 (v) 2.4997 fff8 0 0000 downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 17 right-shifting adc result if the weighting of the adc digital reading must con-form to a predetermined full-scale (pfs) value defined by a standard? specification (e.g., sff-8472), then right-shifting can be used to adjust the pfs analog measurement range while maintaining the weighting of the adc results. the device? range is wide enough to cover all requirements; when the maximum input value is 1/2 of the fs value, right-shifting can be used to obtain greater accuracy. for instance, the maximumvoltage might be 1/8 the specified pfs value, so only 1/8 the converter? range is effective over this range. an alternative is to calibrate the adc? full-scale range to 1/8 the readable pfs value and use a right-shift value of 3. with this implementation, the resolution of the measurement is increased by a factor of 8, and because the result is digitally divided by 8 by right-shifting, the bit weight of the measurement still meets the standard? specification (i.e., sff-8472). the right-shift operation on the adc result is carried out based on the contents of right-shift control registers (table 02h, registers 8eh?fh) in eeprom. three ana- log channels, mon1?on3, each have 3 bits allocated to set the number of right-shifts. up to seven right-shift operations are allowed and are executed as a part of every conversion before the results are compared to the high-alarm and low-alarm levels, or loaded into their corresponding measurement registers (lower memory, registers 64h?bh). this is true during the setup of internal calibration as well as during subsequent data conversions. v cc or gnd referenced mon2 input the device offers a configurable input for mon2.mon2 can either be referenced to v cc or gnd, as shown in figure 6. this enables compatibility with dif-ferent tosa monitor diode configurations. differential mon3 input the device offers a fully differential input for mon3.this enables high-side monitoring of rssi, as shown in figure 7. this reduces board complexity by eliminating the need for a high-side differential amplifier or a cur- rent mirror. DS1878 mon3pmon3n adc 680 rosa v cc figure 7. mon3 differential input for high-side rssi mon2 bmd adc v cc v cc 1k mon2 bmd adc v cc v cc 1k figure 6. mon2 v cc or gnd reference temp v cc mon1 mon2 mon3 mon4 temp one round-robin adc cycle t rr note: if the vcc lo alarm is enabled at power-up, the adc round-robin timing cycles between temperature and v cc only until v cc is above the v cc alarm low threshold. figure 5. adc round-robin timing downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 18 ______________________________________________________________________________________ enhanced rssi monitoring (dual-range functionality) the device offers a feature to improve the accuracyand range of mon3, which is most commonly used for monitoring rssi. using a traditional input, the accuracy of the rssi measurements is increased at the cost of reduced input signal swing. the device eliminates thistrade-off by offering ?ual range?calibration on the mon3 channel. the dual-range calibration can operate in two modes: crossover enabled and crossover disabled. crossover enabled: for systems with a nonlinear relationship between the adc input and desired adcresult, the mode should be set to crossover enabled (figure 8). the rssi measurement of an apd receiv- er is one such application. using the crossover enabled mode allows a piecewise linear approxima- tion of the nonlinear response of the apd? gain fac- tor. the crossover point is the point between fine and coarse points. the adc result transitions between the fine and coarse ranges with no hysteresis. right-shift- ing, slope adjustment, and offset are configurable for both the fine and coarse ranges. the xover fine register determines the maximum results returned by fine adc conversions, before right-shifting. the xover coarse register determines the minimum results returned by coarse adc conversions, before right-shifting. ? crossover disabled: the crossover disabled mode is intended for systems with a linear relationshipbetween the mon3 input and desired adc result. the adc result transitions between the fine and coarse ranges with hysteresis (figure 9). in crossover disabled mode, the thresholds between coarse and fine mode are a function of the number of right-shifts being used. with the use of right-shifting, the fine- mode full scale is programmed to (1/2 nth ) of the coarse-mode full scale. the device now auto rangesto choose the range that gives the best resolution for the measurement. table 4 shows the threshold val- ues for each possible number of right-shifts. crossover point rssi result ideal response mon3 input figure 8. rssi with crossover enabled table 5. mon3 configuration registers register fine mode coarse mode gain 98hC99h, table 02h 9chC9dh, table 02h offset a8hCa9h, table 02h achCadh, table 02h right-shift 0 8fh, table 02h 8fh, table 02h cnfgc (rssi_fc and rssi_ff bits) 8bh, table 02h update (rssir bit) 6fh, lower memory mon3 value 68hC69h, lower memory number of right-shifts fine mode max (hex) coarse mode min* (hex) 0 fff8 f000 1 7ffc 7800 2 3ffe 3c00 3 1fff 1e00 4 0fff 0f00 5 07ff 0780 6 03ff 03c0 7 01ff 01e0 table 4. mon3 hysteresis threshold values* this is the minimum reported coarse-mode conversion. downloaded from: http:///
DS1878 low-voltage operation the device contains two power-on reset (por) levels.the lower level is a digital por (pod) and the higher level is an analog por (poa). at startup, before the supply voltage rises above poa, the outputs are dis- abled, all sram locations are set to their defaults, shadowed eeprom (see) locations are zero, and all analog circuitry is disabled. when v cc reaches poa, the see is recalled, and the analog circuitry is enabled.while v cc remains above poa, the device is in its nor- mal operating state, and it responds based on its non-volatile configuration. if during operation v cc falls below poa, but is still above pod, then the sramretains the see settings from the first see recall, but the device analog is shut down and the outputs disabled. ifthe supply voltage recovers back above poa, then the device immediately resumes normal operation. if the supply voltage falls below pod, then the device sram is placed in its default state and another see recall is required to reload the nonvolatile settings. the eeprom recall occurs the next time v cc exceeds poa. figure 10 shows the sequence of events as thevoltage varies. any time v cc is above pod, the i 2 c interface can be used to determine if v cc is below the poa level. this is accomplished by checking the rdyb bit in the status(lower memory, register 6eh) byte. rdyb is set when v cc is below poa; when v cc rises above poa, rdyb sfp+ controller with digital ldd interface ______________________________________________________________________________________ 19 v poa v pod v cc see recalled value recalled value precharged to 0 precharged to 0 precharged to 0 see recall see recall figure 10. low-voltage hysteresis example rssi result fine full-scale response coarse full-scale response fine right-shift = 3 mon3 input fine coarse hysteresis figure 9. rssi with crossover disabled downloaded from: http:///
DS1878 is timed (within 500?) to go to 0, at which point thepart is fully functional. for all device addresses sourced from eeprom (table 02h, register 8ch), the default device address is a2h until v cc exceeds poa, allowing the device address to be recalled from the eeprom. power-on analog (poa) poa holds the device in reset until v cc is at a suitable level (v cc > poa) for the device to accurately measure with its adc and compare analog signals with its quick- trip monitors. because v cc cannot be measured by the adc when v cc is less than poa, poa also asserts the vcc lo alarm, which is cleared by a v cc adc conver- sion greater than the customer-programmable vcc loadc limit. this allows a programmable limit to ensure that the headroom requirements of the transceiver are satisfied during a slow power-up. the txfout output does not latch until there is a conversion above the vcc lo limit. the poa alarm is nonmaskable. the txf output is asserted when v cc is below poa. see the low-voltage operation section for more information. delta-sigma outputs (dac1 and dac2) two delta-sigma outputs are provided, dac1 anddac2. with the addition of an external rc filter, these outputs provide two 9-bit resolution analog outputs with the full-scale range set by the input refin. each output is either manually controlled or controlled using a tem- perature-indexed lut. a delta-sigma is a digital output using pulse-density modulation. it provides much lower output ripple than a standard digital pwm output given the same clock rate and filter components. before t init , the dac1 and dac2 outputs are high impedance.the external rc filter components are chosen based on ripple requirements, output load, delta-sigma fre- quency, and desired response time. a recommended filter is shown in figure 11. the device? delta-sigma outputs are 9 bits. for illustra- tive purposes, a 3-bit example is provided in figure 12. 20 ______________________________________________________________________________________ DS1878 dac 3.24k 3.24k 0.01 f 0.01 f voltage output DS1878 dac 1k 1k 0.1 f 0.1 f current sink 2k sfp+ controller with digital ldd interface o 12 3 4 5 6 7 figure 12. delta-sigma outputs figure 11. recommended rc filter for dac1/dac2 downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 21 lut loaded to [7:0] lut loaded to [7:0] dac[1/2]ti 8 7 6 5 4 3 2 10 dac[1/2]ti dac[1/2]tc = 0 temperature ( c) -40 +102 temperature ( c) -40 +102 dac[1/2]tc = 1 lut loaded to [8:1] (dac bit 0 = 0) lut loaded to [8:1] (dac bit 0 = 0) delta-sigma daca or dacb 8 7 6 5 4 3 2 10 delta-sigma daca or dacb figure 13. dac1/dac2 lut assignments in lut mode, dac1 and dac2 are each controlled bya separate 8-bit, 4?-resolution, temperature- addressed lut. the delta-sigma outputs use a 10-bit structure. the 8-bit luts are either loaded directly into the msbs (8:1) or the lsbs (7:0). this is determined by dac1ti (table 02h, register c3h), dac2ti (table 02h, register c4h), dac1tc (table 02h, register c6h, bit 6), and dac2tc (table 02h, register c6h, bit 5). see figure 13 for more details. the dac1 lut (table 07h) and dac2 lut (table 08h) registers are nonvolatile and password-2 protected. the reference input, refin, is the supply voltage for the output buffer of dac1 and dac2. the voltage con- nected to refin must be able to support the edge rate requirements of the delta-sigma outputs. in a typical application, a 0.1? capacitor should be connected between refin and ground. digital i/o pins five digital input and four digital output pins are provid-ed for monitoring and control. los, losout by default (losc = 1, table 02h, register 89h), thelos pin is used to convert a standard comparator out- put for loss of signal (los) to an open-collector output. this means the mux shown in the block diagram by default selects the los pin as the source for thelosout output transistor. the output of the mux can be read in the status byte (lower memory, register 6eh) as the rxl bit. the rxl signal can be inverted (inv los = 1) before driving the open-drain output transistor using the xor gate provided. setting losc = 0 configures the mux to be controlled by los lo, which is driven by the output of the los quick trip (table 02h, registers beh and bfh). the mux setting (stored in eeprom) does not take effect until v cc > poa, allowing the eeprom to recall. downloaded from: http:///
DS1878 in1, rsel, rselout the digital input in1 and rsel pins primarily serve tomeet the rate-select requirements of sfp and sfp+. they also serve as general-purpose inputs. rselout is driven by a combination of the rsel and logic dictated by control registers in the eeprom (figure 16). the lev- els of in1 and rsel can be read using the status reg- ister (lower memory, register 6eh). the open-drain rselout output is software-controlled and/or inverted through the status register and cnfga register (table 02h, register 89h). external pullup resistors must be provided on rselout to realize a high logic level. the rsel pin determines the value sent by the 3-wire master to the limiting amplifier? setlos register. when rsel is high, setlosh is used. when rsel is low, setlosl is used. the DS1878 can transmit a bit on the 3-wire bus to register 0x00 (bit 1) of the max3945, max3798, max3799, or rxctrl1 (table 02h, register e8h) within 80ms of a transition (rising or falling) on the rselout. this bit indicates the status of rselout. this feature is user programmable. a bit (rselpin,table 02h, register 89h) is provided to determine whether the i 2 c register rxctrl1 or the status of the rselout pin is transmitted. when rselpin is set to 1,the status of rselout is sent out. rselout is deter- mined by rsel pin, rselc control bit, and invrsout control bit as shown in figure 14. the invrsout bit inverts the rselout bit, and this inversion is reflected when this bit is sent out on the 3- wire bus. figure 14 illustrates the timing for the 3-wire communication when rselpin is set to 1. txd, txdout txdout is generated from a combination of txfout,txd, and the internal signal fetg. a software control identical to txd is available (txdc, lower memory, register 6eh). a txd pulse is internally extended (t initr1 ) to inhibit the latching of low alarms and warn- ings related to the apc loop to allow for the loop to sta-bilize. the nonlatching alarms and warnings are txp sfp+ controller with digital ldd interface 22 ______________________________________________________________________________________ v poa v cc rsel rselout 3w 0x00 bit1 < 1 s < 1 s < 80ms pov = 0 condition: invrsout = 0, rselpin = 1. < 80ms figure 14. 3-wire communication on rselout transition downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 23 lo, los lo, and mon1?on4 lo alarms and warn-ings. in addition, txp lo is disabled from creating fetg. see the transmit fault (txfout) output section for a detailed explanation of txfout. figure 15 showsthat the same signals and faults can also be used to generate the internal signal fetg (table 01h/05h, registers fah?bh). fetg is used to send a fast ?urn- off?command to the laser driver. the status of fteg can be read (lower memory, register 71h). the intend- ed use is a direct connection to the maxim laser driver? txd input if this is desired. when v cc < poa, txdout is high impedance. transmit fault (txfout) output txfout can be triggered by txf input and all alarms,warnings, and quick trips (figure 16). the six adc alarms, warnings, and the los quick trips require enabling (table 01h/05h, registers f8h, fch?dh). see figures 17a and 17b for nonlatched and latched opera- tion. latching of the alarms is controlled by the cnfgb and cnfgc registers (table 02h, registers 8ah?bh). invrsout rselc rsel rsels in1s rselout losc mux los lo rxl setlosctl los inv los in1 losout pins figure 16. logic diagram 2 cc d q q s r out in txds r pu txfs txfouts set bias register and modulation register to 0 txd txfint txp hi flag txp hi enable bias max bias max enable hbal flag hbal enable txp lo flag txp lo enable t initr1 txdc v cc txd txdout txdio txdfg fetg txdflt fault reset timer (130ms) in out power-on reset pins invtxf txf txfout figure 15. logic diagram 1 downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 24 ______________________________________________________________________________________ detection of txf fault txd or txf reset t initr1/2 txfout (only alarm faults present) txfout (qt alarms present) figure 17b. txfout latched operation and txd_txfen = 1 detection of txf fault txfout figure 17a. txfout nonlatched operation by default, txd does not impact txfout (txd_txfen = 0). this is shown in the figure 17c. when txd_txfen = 1, txd affects txfout. the particular behavior is described in figure 17a and 17b. vcctxf is a new control bit is required to enable/dis- able vcc lo alarm/warning before the first v cc con- version is complete. if vcctxf = 1, vcc loalarm/warning does not generate txfout before the first v cc conversion (which takes approximately 13ms to complete). when vcctxf = 0, vcc lo alarm/warn- ing generates txfout before the first v cc conversion, which is illustrated in figure 17c and figure 17d.two conditions are shown. in the first instance, v cc powers on quickly and goes above the vcc lo thresh-old before the first conversion is complete (approxi- mately 13ms). in the other instance, v cc would power up and go above the vcc lo threshold after the first conversion iscomplete. in this case txfout behaves as in figure 17d. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 25 figure 17c. txfout when txd_txfen = 0 on fast power-on v cc vcc lo (assumes vcc lo > v poa ) vcc lo (assumes vcc lo > v poa ) txd or soft txd txfout (1)txfout (2) vcc lo alarm v cc txd or soft txd txfout (1)txfout (2) vcc lo alarm condition 1: vcctxf = 0, any state of vcc lo alarm or warning flag.condition 2: vcctxf = 1, any state of vcc lo alarm or warning flag. condition 1: vcctxf = 0, any state of vcc lo alarm or warning flag. condition 2: vcctxf = 1, any state of vcc lo alarm or warning flag. < 13ms < 13ms downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 26 ______________________________________________________________________________________ figure 17d. txfout when txd_txfen = 0 on slow power-on die identification the DS1878 has an id hardcoded in its die. two regis-ters (table 02h, registers ceh?fh) are assigned for this feature. the ceh register reads 78h to identify the part as the DS1878, while the cfh register reads the current device version. 3-wire master for controlling the maxim laser driver and limiting amplifier the device controls a maxim laser driver and limitingamplifier over a proprietary 3-wire interface. the device acts as the master, initiating communication with and generating the clock for the maxim slave device(s). it is a 3-pin interface consisting of sdaout (a bidirectional data line), sclout (clock signal), and a chip-select output (active high). two chip selects are provided. csel1out is active during all communications. csel2out is only active during communications to the limiting amplifier. by connecting csel2out to a maxim limiting amplifier, there is less noise induced by the communication interface on the limiting amplifier, since none of the laser driver communications are processed by the limiting amplifier. protocol the device initiates a data transfer by asserting thecsel_out pin. it then starts to generate a clock signal after csel_out has been set to 1. each operation consists of 16-bit transfers (15-bit address/data, 1-bit rwn). all data transfers are msb first. write mode (rwn = 0): the master generates 16 clock cycles at sclout in total. it outputs 16 bits (msb first)to the sdaout line at the falling edge of the clock. the master closes the transmission by setting csel_out to 0. read mode (rwn = 1): the master generates 16 clock cycles at sclout in total. it outputs 8 bits (msb first)to the sdaout line at the falling edge of the clock. the sdaout line is released after the rwn bit has been transmitted. the slave outputs 8 bits of data (msb first) at the rising edge of the clock. the master samples sdaout at the falling edge of sclout. the master closes the transmission by setting csel_out to 0. bit name description 15:9 address 7-bit internal register address 8 rwn 0: write; 1: read 7:0 data 8-bit read or write data v poa v cc txd or soft txd* txfout (1)txfout (2) condition 1: vcctxf = 0, vcc lo alarm or warning flag enabled to create txfout.condition 2: vcctxf = 1 and (vcc lo alarm or warning flag is enabled). *don't care about txd state. v cc-lo 13ms < t rr downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 27 csel_out sclout sdaout csel_outnote: see the 3-wire digital interface specification table for details. csel_out implies csel1out or csel2out. sclout sdaout 12345678 a6 9 101112131415 0 1234567891 01 11 21 31 41 5 0 a5 a4 a3 a2 a1 rwn d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 rwn write moderead mode a0 a6 a5 a4 a3 a2 a1 a0 t l t ch t cl t ch t cl t l t ds t dh t ds t rs t dh t t t t figure 18. 3-wire timing 3-wire interface timing figure 18 shows the 3-wire interface timing. figure 19shows the 3-wire state machine. see the 3-wire digital interface specification table for more information. DS1878 master communication interface normal operation the majority of the communications consist of biasadjustments for the apc loop. after each temperature conversion, the laser modulation setting must be updat- ed. all registers are rewritten after every temperature conversion. status registers txstat1 and txstat2 are read between temperature updates at a regular inter- val, t rr (see the analog voltage monitoring characteristics table). the results are stored in 3w txstat1 and 3w txstat2 (table 02h, fch?dh). twochip selects are provided: csel1out and csel2out. in the case where a separate limiting amplifier and laser driver are used, csel2out should be connected to the limiting amplifier. csel2out is only active when receiver-related registers are accessed. this minimizes noise caused by the digital interface. manual operation the master interface is controllable using four registers in the device: 3wctrl, address, write, and read. commands can be manually issued while the device isin normal operation mode. it is also possible to suspend normal 3-wire commands so that only manual operation commands are sent (3wctrl, table 02h, register f8h). initialization during initialization, the device transfers all its 3-wireeeprom control registers to a maxim laser driver and limiting amplifier. the 3-wire control registers include the following: rxctrl1 rxctrl2 setcml setlos txctrl imodmax ibiasmax setpwctl settxde settxeq setlostimer rxctrl3 txctrl2 txctrl3 downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 28 ______________________________________________________________________________________ the control registers are first written once v cc exceeds poa. they are also written after every temperature con-version and on a rising edge of txd. any time one of these events occurs, the device reads and updatestxstat1 and txstat2, and writes set_ibias and set_imod to 0. slave register map and DS1878 corresponding location slave register and address DS1878 register active chip selects register function DS1878 location 00h, rxctrl1 rxctrl1 1 and 2 receiver control table 02h, e8h 01h, rxctrl2 rxctrl2 1 and 2 receiver control table 02h, e9h 02h, rxstat status 1 and 2 receiver status lower memory, 6eh, bit 1 comes from the losout pin (note 1) 03h, set_cml setcml 1 and 2 output cml level setting table 02h, eah 04h, set_los setlosh, setlosl 1 and 2 los assert level settings table 02h, ebh is setlosh, table 02h, f3h is setlosl (note 2) 05h, txctrl txctrl 1 only (note 3) transmitter control table 02h, ech 06h, txstat1 txstat1 1 only (note 3) transmitter status table 02h, fch 07h, txstat2 txstat2 1 only (note 3) transmitter status table 02h, fdh 08h, set_ibias bias 1 only (note 3) bias current setting table 02h, c bhCcch 09h, set_imod modulation 1 only (note 3) modulation current setting table 02h, 82hC83h 0ah, set_imodmax imodmax 1 only (note 3) modulation current limit setting table 02h, edh 0bh, set_ibiasmax ibiasmax 1 only (note 3) bias current limit setting table 02h, eeh 0ch, modinc modinc 1 only (note 3) modulation current dac increment setting automatically written after each temperature conversion. 0dh, biasinc biasinc 1 only (note 3) bias current dac increment setting automatically performed by apc loop. disable apc before using 3-wire manual mode. 0eh, modectrl modectrl 1 and 2 general control (note 1) 0fh, set_pwctrl setpwctrl 1 only (note 3) tx pulse width setting tab le 02h, efh 10h, set_txde settxde 1 only (note 3) tx deemphasis setting table 0 2h, f0h 11h, set_txeq settxeq 1 only (note 3) tx equalization table 02h, f1h 12h, set_lostimer setlostimer 1 and 2 los timer table 02h, f2h 14h, txtm txtm 1 and 2 tx test mode (note 1) 15h, rxtm1 rxtm1 1 and 2 rx test mode (note 1) 16h, rxtm2 rxtm2 1 and 2 rx test mode (note 1) 17h, reserved rxctrl3 1 and 2 receiver control table 02h, f4h 18h, reserved txctrl2 1 only (note 3) transmitter control table 02h, f5h 19h, reserved txctrl3 1 only (note 3) transmitter control table 02h, f6h note 1: this register is not present in the DS1878. to access this register the user must use manual operation (see the manual operation section for details). note 2: either setlosh or setlosl is written to the slave register set_los. this is determined by the signal rsel (see figure 16). note 3: in manual 3-wire mode both chip selects are active for all registers. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 29 por or txd read txpor 3-wire state machine read txpor control/status initialization wait for mod (set mod_flag) write mod (reset flags) txd_standby (set txd_flag) txpor = = 1? manmode = = 1? txd_flag = = 1? or mod_flag = 1? or dis3w = 1? biasinc = = 1? wait for bias read/write manmode standby increment bias control/status update modinc = = 1? biasinc = = 1? temp_conv = = 1? and dis3w = 0 apc_binary = = 0? txd_ext = = 0? txpor = = 1? txd = = 0? txd_flag = = 1? yes yes yes yes yes yes yes yes yes yes yes modinc = = 1? yes dis3w = 1? or bias_manual = 1? txd_flag = = 1? or mod_flag = 1 increment modulation yes yes figure 19. 3-wire state machine downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 30 ______________________________________________________________________________________ sclnote: timing is referenced to v il(max) and v ih(min) . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low figure 20. i 2 c timing i 2 c communication i 2 c definitions the following terminology is commonly used todescribe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device gen-erates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the master? request.bus idle or not busy: time between stop and start conditions when both sda and scl are inac-tive and in their logic-high states. start condition: a start condition is generated by the master to initiate a new data transfer with aslave. transitioning sda from high to low while scl remains high generates a start condition. see figure 20 for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave.transitioning sda from low to high while scl remains high generates a stop condition. see figure 20 for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one datatransfer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address tobegin a data transfer. a repeated start condition is issued identically to a normal start condition. see figure 20 for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain validand unchanged during the entire high pulse of scl plus the setup and hold time requirements (figure 20). data is shifted into the device during the rising edge of the scl. bit read: at the end a write operation, the master must release the sda bus line for the proper amountof setup time (figure 20) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master generates all scl clock pulses, including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowl- edgement (ack) or not acknowledge (nack) isalways the ninth bit transmitted during a byte trans- fer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the ninth bit. a device performs a nack by transmitting a one dur- ing the 9th bit. timing (figure 20) for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 31 sequence or as an indication that the device is notreceiving data. byte write: a byte write consists of 8 bits of informa- tion transferred from the master to the slave (mostsignificant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the master are done according to the bit-write definition and the acknowledgement is read using the bit-read definition. byte read: a byte read is an 8-bit information trans- fer from the slave to the master plus a 1-bit ack ornack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit-read definition, and the master transmits an ack using the bit-write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave returns control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediatelyfollowing a start condition. the slave address byte contains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the device responds to two slave addresses. theauxiliary memory always responds to a fixed i 2 c slave address, a0h. the lower memory and tables00h?8h respond to i 2 c slave addresses that can be configured to any value between 00h?eh using the device address byte (table 02h, register 8ch). the user also must set the asel bit (table 02h, register 89h) for this address to be active. by writing the correct slave address with r/ w = 0, the master indicates it will write data to the slave. if r/ w = 1, the master reads data from the slave. if anincorrect slave address is written, the device assumes the master is communicating with another i 2 c device and ignores the communications until the next start condition is sent. if the main device?slave address is programmed to be a0h, access to the auxiliary memory is disabled. memory address: during an i 2 c write operation to the device, the master must transmit a memoryaddress to identify the memory location where the slave is to store the data. the memory address is always the second byte transmitted during a write operation following the slave address byte. i 2 c protocol writing a single byte to a slave: the master must generate a start condition, write the slave addressbyte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition.remember the master must read the slave? acknowledgement during all byte-write operations. writing multiple bytes to a slave: to write multiple bytes to a slave, the master generates a start con-dition, writes the slave address byte (r/ w = 0), writes the memory address, writes up to 8 databytes, and generates a stop condition. the device writes 1 to 8 bytes (one page or row) with a single write transaction. this is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memo- ry address before each data byte is sent. the address counter limits the write to one 8-byte page (one row of the memory map). attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrapping around to the beginning of the present row. for example, a 3-byte write starts at address 06h and writes 3 data bytes (11h, 22h, and 33h) to three ?onsecutive?addresses. the result is that address- es 06h and 07h would contain 11h and 22h, respec- tively, and the third data byte, 33h, would be written to address 00h. to prevent address wrapping from occurring, the master must send a stop condition at the end of the page, then wait for the bus-free or eeprom write time to elapse. then the master can generate a new start condition and write the slave address byte (r/ w = 0) and the first memory address of the next memory row before continuing to write data.acknowledge polling: any time a eeprom page is written, the device requires the eeprom write time(t wr ) after the stop condition to write the contents of the page to eeprom. during the eeprom writetime, the device does not acknowledge its slave address because it is busy. it is possible to take advantage of that phenomenon by repeatedly addressing the device, which allows the next page to be written as soon as the device is ready to receive the data. the alternative to acknowledge polling is to wait for maximum period of t wr to elapse before attempting to write again to the device.eeprom write cycles: when eeprom writes occur, the device writes the whole eeprom memory page, even if only a single byte on the page was modified.writes that do not modify all 8 bytes on the page are allowed and do not corrupt the remaining bytes of memory on the same page. because the whole page is written, bytes on the page that were not modified during the transaction are still subject to a write downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 32 ______________________________________________________________________________________ start start stop slave ack slave ack stop single-byte write-write 00h to register bah two-byte write -write 01h and 75h to c8h and c9h single-byte read-read register bah two-byte read -read c8h and c9h repeated start master nack 10100010 a2h 10111010 bah slave ack start slave ack 10100010 a2h 10100011 a3h 10111010 bah slave ack slave ack stop 00000000 00h stop slave ack stop 01110101 75h start slave ack 10100010 a2h 11001000 c8h slave ack slave ack 00000001 01h slave ack data in bah data repeated start master ack start slave ack 10100010 a2h 10100011 a3h 11001000 c8h slave ack slave ack data in c8h data master nack data in c9h data example i 2 c transactions with a2h as the main memory device address *if asel is 0, the slave address is a0h for the auxiliary memory and a2h for the main memory. if asel = 1, the slave address is determined by table 02h, register 8ch for the main memory. the auxiliary memory continues to be addressed at a0h, except when the programmed address for the main memory is a0h. typical i 2 c write transaction a)c) b)d) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 register address msb lsb b7 b6 b5 b4 b3 b2 b1 b0 data slave ack slave ack slave address* 1 0 1 0 0 0 1 r/w msb lsb read/ write figure 21. example i 2 c timing cycle. this can result in a whole page being worn outover time by writing a single byte repeatedly. writing a page one byte at a time wears the eeprom out eight times faster than writing the entire page at once. the device? eeprom write cycles are speci- fied in the nonvolatile memory characteristics table. the specification shown is at the worst-case temper-ature. it can handle approximately ten times that many writes at room temperature. writing to sram- shadowed eeprom memory with seeb = 1 does not count as an eeprom write cycle when evaluating the eeprom? estimated lifetime. reading a single byte from a slave: unlike the write operation that uses the memory address byteto define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of thetransfer, and generates a stop condition. manipulating the address counter for reads: a dummy write cycle can be used to force the addresspointer to a particular value. to do this, the master generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeatedstart condition, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable,and generates a stop condition. memory organization the device features nine separate memory tables thatare internally organized into 8-byte rows. the lower memory is addressed from 00h?fh and contains alarm and warning thresholds, flags, masks,several control registers, password entry area (pwe), and the table-select byte. table 01h primarily contains user eeprom (with pw1 level access) as well as alarm and warning-enablebytes. table 02h is a multifunction space that contains config- uration registers, scaling and offset values, passwords,interrupt registers as well as other miscellaneous con- trol bytes. table 04h contains a temperature-indexed lut for control of the modulation voltage. the modulation lutcan be programmed in 2? increments over the -40? to +102? range. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 33 table 05h is empty by default. it can be configured to contain the alarm- and warning-enable bytes from table 01h, registers f8h?fh with the mask bit enabled (table 02h, register 89h). in this case table 01h is empty. table 06h contains a temperature-indexed lut that allows the apc set point to change as a function oftemperature to compensate for te. the apc lut has 36 entries that determine the apc setting in 4? win- dows between -40? and +100?. table 07h contains a temperature-indexed lut for con- trol of dac1. the lut has 36 entries that determine thedac setting in 4? windows between -40? and +100?. table 08h contains a temperature-indexed lut for con- trol of dac2. the lut has 36 entries that determine thedac setting in 4? windows between -40? and +100?. auxiliary memory (device a0h) contains 256 bytes of ee memory accessible from address 00h?fh. it isselected with the device address of a0h. see the register descriptions section for more com- plete details of each byte? function, as well as forread/write permissions for each byte. shadowed eeprom many nv memory locations (listed within the register descriptions section) are actually shadowed eeprom that are controlled by the seeb bit in table 02h,register 80h. the device incorporates shadowed-eeprom memory locations for key memory addresses that can be writ- ten many times. by default the shadowed-eeprom bit, seeb, is not set and these locations act as ordinary eeprom. by setting seeb, these locations function like sram cells, which allow an infinite number of write cycles without concern of wearing out the eeprom. setting seeb also eliminates the requirement for the eeprom write time, t wr . because changes made with seeb enabled do not affect the eeprom, thesechanges are not retained through power cycles. the power-on value is the last value written with seeb dis- abled. this function can be used to limit the number of eeprom writes during calibration or to change the monitor thresholds periodically during normal opera- tion helping to reduce the number of times eeprom is written. eeprom (256 bytes) ffh i 2 c address a0h i 2 c address a2h (default) auxiliary device main device 00h alarm- enable row (8 bytes) password entry (pwe) (4 bytes) table-select byte ffh 80hf8h table 01h eeprom (120 bytes) f7h 7fh 00h lower memory 3w config ffh 80he8h table 02h nonlookup table control and configuration registers e7h 80h table 04h mod lut (72 bytes) c7h f8h table 05h alarm-enable row (8 bytes) ffh 80h table 06h apc lut (36 bytes) a3h 80h table 07h dac1 lut (36 bytes) a3h 80h table 08h dac2 lut (36 bytes) a3h note 1: if asel = 0, then the main device i 2 c slave address is a2h. if asel = 1, then the main device i 2 c slave address is determined by the value in table 02h, register 8ch. note 2: table 00h does not exist. note 3: alarm-enable row can be configured to exist at table 01h or table 05h using the mask bit in table 02h, register 89h. figure 22. memory map downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 34 ______________________________________________________________________________________ register descriptions the register maps show each byte/word (2 bytes) in terms of its row in the memory. the first byte in the row is locat-ed in memory at the row address (hexadecimal) in the leftmost column. each subsequent byte on the row is one/two memory locations beyond the previous byte/word? address. a total of 8 bytes are present on each row. for more information about each of these bytes see the corresponding register description. lower memory register map lower memory word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 00 <1> threshold 0 temp alarm hi temp alarm lo temp warn hi temp warn lo 08 <1> threshold 1 v cc alarm hi v cc alarm lo v cc warn hi v cc warn lo 10 <1> threshold 2 mon1 alarm hi mon1 alarm lo mon1 warn hi mon1 warn lo 18 <1> threshold 3 mon2 alarm hi mon2 alarm lo mon2 warn hi mon2 warn lo 20 <1> threshold 4 mon3 alarm hi mon3 alarm lo mon3 warn hi mon3 warn lo 28 <1> threshold 5 mon4 alarm hi mon4 alarm lo mon4 warn hi mon4 warn lo 30C5f <1> eeprom ee ee ee ee ee ee ee ee 60 <2> adc values 0 temp value v cc value mon1 value mon2 value 68 <0> adc values 1 <2> mon3 value <2> mon4 value <2> reserved <0> status <3> update 70 <2> alarm/ warn alarm 3 alarm 2 alarm 1 alarm 0 warn 3 warn 2 reserved 78 <0> table select <2> reserved <2> reserved <6> pwe msw <6> pwe lsw <5> tbl sel access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and device hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 the access codes represent the factory default values of pw_ena and pw_enb (table 02h, registers c0h?1h). downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 35 table 01h register map the alarm enable bytes (registers f8h?fh) can be configured to exist in table 05h instead of here at table 01h with the mask bit (table 02h, register 89h). if the row is configured to exist in table 05h, then these locations are empty in table 01h. the access codes represent the factory default values of pw_ena and pw_enb (table 02h, registers c0h?1h). table 01h word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80Cbf <7> eeprom ee ee ee ee ee ee ee ee c0Cf7 <8> eeprom ee ee ee ee ee ee ee ee f8 <8> alarm enable alarm en 3 alarm en 2 alarm en 1 alarm en 0 warn en 3 warn en 2 reserved reserved access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and device hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 36 ______________________________________________________________________________________ table 02h register map table 02h (pw2) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80 <0> config 0 <8> mode <4> tindex <4> modulation register <4> dac1 value <4> dac2 value 88 <8> config 1 sample rate cnfga cnfgb cnfgc device address reserved rshift 1 rshift 0 90 <8> scale 0 xover coarse v cc scale mon1 scale mon2 scale 98 <8> scale 1 mon3 fine scale mon4 scale mon3 coarse scale reserved a0 <8> offset 0 xover fine v cc offset mon1 offset mon2 offset a8 <8> offset 1 mon3 fine offset mon4 offset mon3 coarse offset internal temp offset* b0 <9> pwd value pw1 msw pw1 lsw pw2 msw pw2 lsw b8 <8> threshold los ranging comp ranging isteph istepl htxp ltxp hlos llos c0 <8> pwd enable pw_ena pw_enb modti dac1ti dac2ti istepti luttc tblselpon c8 <0> apc <4> man bias <4> man_ cntl <10> bias register <4> apc dac <10> device id <10> device ver d0 <8> hbath lut hbath hbath hbath hbath hbath hbath hbath hbath d8Ce7 empty empty empty empty empty empty empty empty empty e8 <8> 3w config 0 rxctrl1 rxctrl2 setcml setlosl txctrl imodmax ibiasmax setpwctrl f0 <8> 3w config 1 settxde settxeq setlostimer setlosh rxctrl3 txctrl2 txctrl3 3wset f8 <0> 3w config 2 <8> 3wctrl <8> address <8> write <10> read <10> txstat1 <10> txstat2 reserved reserved access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and device hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 * the final result must be xored with bb40h before writing to this register. * do not write to this register. the access codes represent the factory default values of pw_ena and pw_enb (table 02h, registers c0h?1h). downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 37 table 04h register map table 04h (modulation lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80Cc7 <8> lut4 mod mod mod mod mod mod mod mod access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and device hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 table 05h register map table 05h is empty by default. it can be configured to contain the alarm and warning-enable bytes from table 01h,registers f8h?fh with the mask bit enabled (table 02h, register 89h). in this case table 01h is empty. table 05h word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80Cf7 empty empty empty empty empty empty empty empty empty f8 <8> alarm enable alarm en 3 alarm en 2 alarm en 1 alarm en 0 warn en 3 warn en 2 reserved reserved table 06h register map the access codes represent the factory default values of pw_ena and pw_enb (table 02h, registers c0h?1h). table 06h (apc lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80C9f <8> apc lut apc ref apc ref apc ref apc ref apc ref apc ref apc ref apc ref a0 <8> apc lut apc ref apc ref apc ref apc ref reserved reserved reserved reserved downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 38 ______________________________________________________________________________________ table 08h register map table 07h (dac1 lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80C9f <8> lut7 dac1 dac1 dac1 dac1 dac1 dac1 dac1 dac1 a0 <8> lut7 dac1 dac1 dac1 dac1 reserved reserved reserved reserved access code <0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11> read access all all all pw2 all n/a pw1 pw2 n/a pw2 all write access see each bit/byte separately pw2 n/a all and device hardware pw2 + mode bit all all pw1 pw2 pw2 n/a pw1 table 08h (dac2 lut) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 80C9f <8> lut8 dac2 dac2 dac2 dac2 dac2 dac2 dac2 dac2 a0 <8> lut8 dac2 dac2 dac2 dac2 reserved reserved reserved reserved table 07h register map auxiliary a0h memory register map the access codes represent the factory default values of pw_ena and pw_enb (table 02h, registers c0h?1h). auxiliary memory (a0h) word 0 word 1 word 2 word 3 row (hex) row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 00Cff <5> aux ee ee ee ee ee ee ee ee ee downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 39 lower memory register descriptions lower memory, register 00h?1h: temp alarm hilower memory, register 04h?5h: temp warn hi factory default 7fffh read access all write access pw2 memory type nonvolatile (see) 00h, 04h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 01h, 05h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit 7 bit 0 temperature measurement updates above this twos complement threshold set co rresponding alarm or warning bits. temperature measurement updates equal to or below this threshol d clear alarm or warning bits. lower memory, register 02h?3h: temp alarm lolower memory, register 06h?7h: temp warn lo factory default 8000h read access all write access pw2 memory type nonvolatile (see) 02h, 06h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 03h, 07h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit 7 bit 0 temperature measurement updates below this twos complement threshold set cor responding alarm or warning bits. temperature measurement updates equal to or above this threshold clear alarm or warning bits. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 40 ______________________________________________________________________________________ lower memory, register 08h?9h: v cc alarm hi lower memory, register 0ch?dh: v cc warn hi lower memory, register 10h?1h: mon1 alarm hilower memory, register 14h?5h: mon1 warn hi lower memory, register 18h?9h: mon2 alarm hi lower memory, register 1ch?dh: mon2 warn hi lower memory, register 20h?1h: mon3 alarm hi lower memory, register 24h?5h: mon3 warn hi lower memory, register 28h?9h: mon4 alarm hi lower memory, register 2ch?dh: mon4 warn hi factory default ffffh read access all write access pw2 memory type nonvolatile (see) 08h, 0ch, 10h, 14h, 18h, 1ch, 20h, 24h, 28h, 2ch 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 09h, 0dh, 11h, 15h, 19h, 1dh, 21h, 25h, 29h, 2dh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 voltage measurement updates above this unsigned threshold set corresponding alarm or warning bits. voltage measurements equal to or below this threshold clear alarm or warning bits. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 41 lower memory, register 0ah?bh: v cc alarm lo lower memory, register 0eh?fh: v cc warn lo lower memory, register 12h?3h: mon1 alarm lolower memory, register 16h?7h: mon1 warn lo lower memory, register 1ah?bh: mon2 alarm lo lower memory, register 1eh?fh: mon2 warn lo lower memory, register 22h?3h: mon3 alarm lo lower memory, register 26h?7h: mon3 warn lo lower memory, register 2ah?bh: mon4 alarm lo lower memory, register 2eh?fh: mon4 warn lo factory default 0000h read access all write access pw2 memory type nonvolatile (see) 0ah, 0eh, 12h, 16h, 1ah, 1eh, 22h, 26h, 2ah, 2eh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 0bh, 0fh, 13h, 17h, 1bh, 1fh, 23h, 27h, 2bh, 2fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 voltage measurement updates below this unsigned threshold set corres ponding alarm or warning bits. voltage measurements equal to or above this threshold clear alarm or warning bi ts. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 42 ______________________________________________________________________________________ lower memory, register 30h?fh: ee factory default 00h read access all write access pw2 memory type nonvolatile (ee) 30hC5fh ee ee ee ee ee ee ee ee bit 7 bit 0 pw2 level access-controlled eeprom. power-on value 0000h read access all write access n/a memory type volatile 60h s 2 6 2 5 2 4 2 3 2 2 2 1 2 0 61h 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 bit 7 bit 0 signed twos complement direct-to-temperature measurement. lower memory, register 60h?1h: temp value downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 43 lower memory, register 6ch?dh: reserved power-on value 00h read access all write access n/a memory type these registers are reserved. power-on value 0000h read access all write access n/a memory type volatile 62h, 64h, 66h, 68h, 6ah 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 63h, 65h, 67h, 69h, 6bh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 left-justified unsigned voltage measurement. lower memory, register 62h?3h: v cc value lower memory, register 64h?5h: mon1 valuelower memory, register 66h?7h: mon2 value lower memory, register 68h?9h: mon3 value lower memory, register 6ah?bh: mon4 value downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 44 ______________________________________________________________________________________ power-on value x0xx 0xxxb read access all write access see below memory type volatile write access n/a all n/a all all n/a n/a n/a 6eh txds txdc in1s rsels rselc txfouts rxl rdyb bit 7 bit 0 bit 7 txds: txd status bit. reflects the logic state of the txd pin (read only). 0 = txd pin is logic-low. 1 = txd pin is logic-high. bit 6 txdc: txd software control bit. this bit allows for software control that is identical to the txd pin. see the section on txd for further information. its value is wire-ored with th e logic value of the txd pin (writable by all users). 0 = (default). 1 = forces the device into a txd state regardless of the value of the txd p in. bit 5 in1s: in1 status bit. reflects the logic state of the in1 pin (read only). 0 = in1 pin is logic-low. 1 = in1 pin is logic-high. bit 4 rsels: rsel status bit. reflects the logic state of the rsel pin (read only ). 0 = rsel pin is logic-low. 1 = rsel pin is logic-high. bit 3 rselc: rsel software control bit. this bit allows for software control that is identical to the rsel pin. its value is wire-ored with the logic value of the rsel p in to create the rselout pins logic value (writable by all users). 0 = (default). 1 = forces the device into a rsel state regardless of the value of t he rsel pin. bit 2 txfouts: txfout status. indicates the state the open-drain output is attempting to achie ve. 0 = txfout is pulling low. 1 = txfout is high impedance. bit 1 rxl: reflects the driven state of the losout pin (read only). 0 = losout pin is driven low. 1 = losout pin is pulled high. bit 0 rdyb: ready bar. 0 = v cc is above poa. 1 = v cc is below poa and/or too low to communicate over the i 2 c bus. lower memory, register 6eh: status downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 45 lower memory, register 6fh: update power-on value 00h read access all write access all and device hardware memory type volatile 6fh temp rdy vcc rdy mon1 rdy mon2 rdy mon3 rdy mon4 rdy reserved rssir bit 7 bit 0 bits 7:2 update of completed conversions. at power-on, these bits are cleared and are set as each conversion is completed. these bits can be cleared so that a completion of a new convers ion is verified. bit 1 reserved bit 0 rssir: rssi range. reports the range used for conversion update of mon3. 0 = fine range is the reported value. 1 = coarse range is the reported value. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 46 ______________________________________________________________________________________ power-on value 10h read access all write access n/a memory type volatile 70h temp hi temp lo vcc hi vcc lo mon1 hi mon1 lo mon2 hi mon2 lo bit 7 bit 0 bit 7 temp hi: high-alarm status for temperature measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 6 temp lo: low-alarm status for temperature measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 5 vcc hi: high-alarm status for v cc measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 4 vcc lo: low-alarm status for v cc measurement. this bit is set when the v cc supply is below the poa trip point value. it clears itself when a v cc measurement is completed and the value is above the low threshold. 0 = last measurement was equal to or above threshold setting. 1 = (default) last measurement was below threshold setting. bit 3 mon1 hi: high-alarm status for mon1 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 2 mon1 lo: low-alarm status for mon1 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 1 mon2 hi: high-alarm status for mon2 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 0 mon2 lo: low-alarm status for mon2 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. lower memory, register 70h: alarm 3 downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 47 lower memory, register 71h: alarm 2 power-on value 00h read access all write access n/a memory type volatile 71h mon3 hi mon3 lo mon4 hi mon4 lo reserved txfs fetg txfint bit 7 bit 0 bit 7 mon3 hi: high-alarm status for mon3 measurement. a txd event does not clea r this alarm. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 6 mon3 lo: low-alarm status for mon3 measurement. a txd event does not clear this alarm. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 5 mon4 hi: high-alarm status for mon4 measurement. a txd event does not clea r this alarm. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 4 mon4 lo: low-alarm status for mon4 measurement. a txd event does not clear this alarm. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 3 reserved bit 2 txfs: reflects the status of the txf pin. the status also includes any inve rsion caused by the invtxf bit (read only). 0 = txf pin is low (after any inversion caused by the invtxf bit). 1 = txf pin is high (after any inversion caused by the invtxf bit). bit 1 fetg: status of internal signal fetg. the fetg signal is part of the internal shutdown logic. 0 = fetg is low. 1 = fetg is high. bit 0 txfint: txfout interrupt. this bit is the wire-ored logic of all alarms and war nings wire-anded with their corresponding enable bits in addition to nonmaskable alarms tx p hi, txp lo, bias max, and hbal. the enable bits are found in table 01h/05h, registers f8hCffh. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 48 ______________________________________________________________________________________ lower memory, register 72h: alarm 1 power-on value 00h read access all write access n/a memory type volatile 72h reserved reserved reserved reserved hbal reserved txp hi tx p lo bit 7 bit 0 bits 7:4 reserved bit 3 hbal: high-bias alarm status; fast comparison. a txd event clears this alarm. 0 = (default) last comparison was below threshold setting. 1 = last comparison was above threshold setting. bit 2 reserved bit 1 txp hi: high-alarm status txp; fast comparison. a txd event clears this a larm. 0 = (default) last comparison was below threshold setting. 1 = last comparison was above threshold setting. bit 0 txp lo: low-alarm status txp; fast comparison. a txd event clears this al arm. 0 = (default) last comparison was above threshold setting. 1 = last comparison was below threshold setting. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 49 power-on value 00h read access all write access n/a memory type volatile 73h los hi los lo reserved reserved bias max reserved reserved reserved bit 7 bit 0 bit 7 los hi: high-alarm status for mon3; fast comparison. a txd event does not clear this alarm. 0 = (default) at por, this is the state if the last comparison was below the hlos threshold setting. see the description of the set condition to determine what causes los hi to be reset. 1 = last comparison was above the hlos threshold setting. los hi st ays set until the time mon3 goes below the llos level, or a por to the device causes los hi to reset if it i s below the hlos threshold. bit 6 los lo: low-alarm status for mon3; fast comparison. a txd event does no t clear this alarm. 0 = (default) at por, this is the state if the last comparison was ab ove the llos threshold setting. see the description of the set condition to determine what causes los lo to be reset. 1 = last comparison was below the llos threshold setting. los l o stays set until the time mon3 goes above the hlos level, or a por to the device causes los lo to reset if it i s below the llos threshold. bits 5:4 reserved bit 3 bias max: alarm status for maximum digital setting of bias. a txd event clears this alarm. 0 = (default) the value for bias is equal to or below the ibiasmax re gister. 1 = requested value for bias is greater than the ibiasmax register. bits 2:0 reserved lower memory, register 73h: alarm 0 downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 50 ______________________________________________________________________________________ lower memory, register 74h: warn 3 power-on value 10h read access all write access n/a memory type volatile 74h temp hi temp lo vcc hi vcc lo mon1 hi mon1 lo mon2 hi mon2 lo bit 7 bit 0 bit 7 temp hi: high-warning status for temperature measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 6 temp lo: low-warning status for temperature measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 5 vcc hi: high-warning status for v cc measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 4 vcc lo: low-warning status for v cc measurement. this bit is set when the v cc supply is below the poa trip point value. it clears itself when a v cc measurement is completed and the value is above the low threshold. 0 = last measurement was equal to or above threshold setting. 1 = (default) last measurement was below threshold setting. bit 3 mon1 hi: high-warning status for mon1 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 2 mon1 lo: low-warning status for mon1 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 1 mon2 hi: high-warning status for mon2 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 0 mon2 lo: low-warning status for mon2 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 51 lower memory, register 75h: warn 2 power-on value 00h read access all write access n/a memory type volatile 75h mon3 hi mon3 lo mon4 hi mon4 lo reserved reserved reserve d reserved bit 7 bit 0 bit 7 mon3 hi: high-warning status for mon3 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 6 mon3 lo: low-warning status for mon3 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bit 5 mon4 hi: high-warning status for mon4 measurement. 0 = (default) last measurement was equal to or below threshold setting. 1 = last measurement was above threshold setting. bit 4 mon4 lo: low-warning status for mon4 measurement. 0 = (default) last measurement was equal to or above threshold setting. 1 = last measurement was below threshold setting. bits 3:0 reserved power-on value 00h read access n/a write access n/a memory type these registers are reserved. lower memory, register 76h?ah: reserved downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 52 ______________________________________________________________________________________ lower memory, register 7bh?eh: password entry (pwe) power-on value ffff ffffh read access n/a write access all memory type volatile 7bh 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 7ch 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 7dh 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 7eh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 there are two passwords for the device. each password is 4 bytes long. the lower le vel password (pw1) has all the access of a normal user plus those made available with pw1. the higher l evel password (pw2) has all the access of pw1 plus those made available with pw2. the values of the passw ords reside in eeprom inside pw2 memory. at power-up, all pwe bits are set to 1. all reads at this location are 0. power-on value tblselpon (table 02h, register c7h) read access all write access all memory type volatile 7fh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the upper memory tables of the device are accessible by writing the desired tab le value in this register. the power-on value of this register is defined by the value written to tblselpon (ta ble 02h, register c7h). lower memory, register 7fh: table select (tbl sel) downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 53 table 01h register descriptions table 01h, register 80h?fh: eeprom power-on value 00h read access pw2 or (pw1 and rwtbl1a) or (pw1 and rtbl1a) write access pw2 or (pw1 and rwtbl1a) memory type nonvolatile (ee) 80hCbfh ee ee ee ee ee ee ee ee bit 7 bit 0 eeprom for pw1 and/or pw2 level access. power-on value 00h read access pw2 or (pw1 and rwtbl1b) or (pw1 and rtbl1b) write access pw2 or (pw1 and rwtbl1b) memory type nonvolatile (ee) c0hCf7h ee ee ee ee ee ee ee ee bit 7 bit 0 eeprom for pw1 and/or pw2 level access. table 01h, register c0h?7h: eeprom downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 54 ______________________________________________________________________________________ table 01h, register f8h: alarm en 3 power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) memory type nonvolatile (see) f8h temp hi temp lo vcc hi vcc lo mon1 hi mon1 lo mon2 hi mon2 lo bit 7 bit 0 layout is identical to alarm 3 in lower memory, register 70h. enables alarms to create txfint (lower memory, register 71h) logic. the mask bit (table 02h, register 89h) determines whether this me mory exists in table 01h or 05h. bit 7 temp hi: 0 = disables interrupt from temp hi alarm. 1 = enables interrupt from temp hi alarm. bit 6 temp lo: 0 = disables interrupt from temp lo alarm. 1 = enables interrupt from temp lo alarm. bit 5 vcc hi: 0 = disables interrupt from vcc hi alarm. 1 = enables interrupt from vcc hi alarm. bit 4 vcc lo: 0 = disables interrupt from vcc lo alarm. 1 = enables interrupt from vcc lo alarm. bit 3 mon1 hi: 0 = disables interrupt from mon1 hi alarm. 1 = enables interrupt from mon1 hi alarm. bit 2 mon1 lo: 0 = disables interrupt from mon1 lo alarm. 1 = enables interrupt from mon1 lo alarm. bit 1 mon2 hi: 0 = disables interrupt from mon2 hi alarm. 1 = enables interrupt from mon2 hi alarm. bit 0 mon2 lo: 0 = disables interrupt from mon2 lo alarm. 1 = enables interrupt from mon2 lo alarm. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 55 table 01h, register f9h: alarm en 2 power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) memory type nonvolatile (see) f9h mon3 hi mon3 lo mon4 hi mon4 lo reserved reserved reserve d reserved bit 7 bit 0 layout is identical to alarm 2 in lower memory, register 71h. enables alarms to create txfint (lower memory, register 71h) logic. the mask bit (table 02h, register 89h) determines whether this memory exists in table 01h or 05h. bit 7 mon3 hi: 0 = disables interrupt from mon3 hi alarm. 1 = enables interrupt from mon3 hi alarm. bit 6 mon3 lo: 0 = disables interrupt from mon3 lo alarm. 1 = enables interrupt from mon3 lo alarm. bit 5 mon4 hi: 0 = disables interrupt from mon4 hi alarm. 1 = enables interrupt from mon4 hi alarm. bit 4 mon4 lo: 0 = disables interrupt from mon4 lo alarm. 1 = enables interrupt from mon4 lo alarm. bit 3:0 reserved downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 56 ______________________________________________________________________________________ table 01h, register fah: alarm en 1 power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) memory type nonvolatile (see) fah reserved reserved reserved reserved hbal reserved txp hi tx p lo bit 7 bit 0 layout is identical to alarm 1 in lower memory, register 72h. enables alarms to create internal signal fetg (see figure 15) logic. the mask bit (table 02h, register 89h) determi nes whether this memory exists in table 01h or 05h. bits 7:4 reserved bit 3 hbal: 0 = disables interrupt from hbal alarm. 1 = enables interrupt from hbal alarm. bit 2 reserved bit 1 txp hi: 0 = disables interrupt from txp hi alarm. 1 = enables interrupt from txp hi alarm. bit 0 txp lo: 0 = disables interrupt from txp lo alarm. 1 = enables interrupt from txp lo alarm. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 57 table 01h, register fbh: alarm en 0 power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) memory type nonvolatile (see) fbh los hi los lo reserved reserved bias max reserved reserved re served bit 7 bit 0 layout is identical to alarm 0 in lower memory, register 73h. the mask bit (table 02h, register 89h) determines whether this memory exists in table 01h or 05h. bit 7 los hi: enables alarm to create txfint (lower memory, register 71h) logic. 0 = disables interrupt from los hi alarm. 1 = enables interrupt from los hi alarm. bit 6 los lo: enables alarm to create txfint (lower memory, register 71h) logic. 0 = disables interrupt from los lo alarm. 1 = enables interrupt from los lo alarm. bits 5:4 reserved bit 3 bias max: enables alarm to create internal signal fetg (see figure 15) logic. 0 = disables interrupt from bias max alarm. 1 = enables interrupt from bias max alarm. bits 2:0 reserved downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 58 ______________________________________________________________________________________ table 01h, register fch: warn en 3 power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) memory type nonvolatile (see) f8h temp hi temp lo vcc hi vcc lo mon1 hi mon1 lo mon2 hi mon2 lo bit 7 bit 0 layout is identical to warn 3 in lower memory, register 74h. enables warnings to create txfint (lower memory, register 71h) logic. the mask bit (table 02h, register 89h) determines whether this me mory exists in table 01h or 05h. bit 7 temp hi: 0 = disables interrupt from temp hi warning. 1 = enables interrupt from temp hi warning. bit 6 temp lo: 0 = disables interrupt from temp lo warning. 1 = enables interrupt from temp lo warning. bit 5 vcc hi: 0 = disables interrupt from vcc hi warning. 1 = enables interrupt from vcc hi warning. bit 4 vcc lo: 0 = disables interrupt from vcc lo warning. 1 = enables interrupt from vcc lo warning. bit 3 mon1 hi: 0 = disables interrupt from mon1 hi warning. 1 = enables interrupt from mon1 hi warning. bit 2 mon1 lo: 0 = disables interrupt from mon1 lo warning. 1 = enables interrupt from mon1 lo warning. bit 1 mon2 hi: 0 = disables interrupt from mon2 hi warning. 1 = enables interrupt from mon2 hi warning. bit 0 mon2 lo: 0 = disables interrupt from mon2 lo warning. 1 = enables interrupt from mon2 lo warning. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 59 table 01h, register fdh: warn en 2 power-on value 00h read access pw2 or (pw1 and rwtbl1c) or (pw1 and rtbl1c) write access pw2 or (pw1 and rwtbl1c) memory type nonvolatile (see) f9h mon3 hi mon3 lo mon4 hi mon4 lo reserved reserved reserve d reserved bit 7 bit 0 layout is identical to warn 2 in lower memory, register 75h. enables warnings to create txfint (lower memory, register 71h) logic. the mask bit (table 02h, register 89h) determines whet her this memory exists in table 01h or 05h. bit 7 mon3 hi: 0 = disables interrupt from mon3 hi warning. 1 = enables interrupt from mon3 hi warning. bit 6 mon3 lo: 0 = disables interrupt from mon3 lo warning. 1 = enables interrupt from mon3 lo warning. bit 5 mon4 hi: 0 = disables interrupt from mon4 hi warning. 1 = enables interrupt from mon4 hi warning. bit 4 mon4 lo: 0 = disables interrupt from mon4 lo warning. 1 = enables interrupt from mon4 lo warning. bits 3:0 reserved power-on value 00h read access n/a write access n/a memory type nonvolatile (see) these registers are reserved. table 01h, register feh?fh: reserved downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 60 ______________________________________________________________________________________ table 02h register descriptions table 02h, register 80h: mode power-on value 3fh read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rtbl246) memory type volatile 80h seeb reserved dac1 en dac2 en aen mod en apc en bias en bit 7 bit 0 bit 7 seeb: 0 = (default) enables eeprom writes to see bytes. 1 = disables eeprom writes to see bytes during configuration, so that the configuration of the part is not delayed by the ee cycle time. once the values are known, write this bit t o a 0 and write the see locations again for data to be written to the eeprom. bit 6 reserved bit 5 dac1 en: 0 = dac1 value is writable by the user and the lut recalls are disabled. this allows users to interactively test their modules by writing the values for dac1. the output is updated with the new value at the end of the write cycle. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables auto control of the lut for dac1 value. bit 4 dac2 en: 0 = dac2 value is writable by the user and the lut recalls are disabled. this allows users to interactively test their modules by writing the values for dac2. the output is updated with the new value at the end of the write cycle. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables auto control of the lut for dac2 value. bit 3 aen: 0 = the temperature-calculated index value tindex is writable by users and the updates of calculated indexes are disabled. this allows users to interactively test their modules by controlling the indexing for the luts. the recalled values from the lut s appear in the dac registers after the next completion of a temperature conversion. 1 = (default) the internal temperature sensor determines the value of tindex. bit 2 mod en: 0 = modulation register is writable by the user and the lut recall s are disabled. this allows users to interactively test their modules by writing the dac value for mo dulation. the output is updated with the new value at the end of the write cycle. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables auto control of the lut for modulation. bit 1 apc en: 0 = apc dac is writable by the user and the lut recalls are disabled. thi s allows users to interactively test their modules by writing the dac value for apc refe rence. the output is updated with the new value at the end of the write cycle through the 3-wire interface. the i 2 c stop condition is the end of the write cycle. 1 = (default) enables auto control of the lut for apc reference. bit 0 bias en: 0 = bias register is controlled by the user and the apc is in manual mode. the bias r egister value is written with the use of the 3-wire interface. this allows the user to interactiv ely test their modules by writing the dac value for bias. 1 = (default) enables auto control for the apc feedback. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 61 table 02h, register 81h: temperature index (tindex) factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access (pw2 and aen = 0) or (pw1 and rwtbl246 and aen = 0 ) memory type volatile 81h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 holds the calculated index based on the temperature measurement. this index is us ed for the address during lookup of tables 04h, 06hC08h. temperature measurements below -40 c or above +102c are clamped to 80h and c7h, respectively. the calculation of tindex is as follows: tindex = temp _ value + 40 c 2 c + 80h for the temperature-indexed luts, the index used during the lookup function for each table i s as follows: table 04h (mod) 1 tindex 6 tindex 5 tindex 4 tindex 3 tindex 2 tindex 1 tindex 0 table 06h (apc) 1 0 tindex 6 tindex 5 tindex 4 tindex 3 tindex 2 tindex 1 table 07h (dac1) 1 0 tindex 6 tindex 5 tindex 4 tindex 3 tindex 2 tindex 1 table 08h (dac2) 1 0 tindex 6 tindex 5 tindex 4 tindex 3 tindex 2 tindex 1 factory default 0000h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access (pw2 and mod en = 0) or (pw1 and rwtbl246 and mod en = 0) memory type volatile 82h 0 0 0 0 0 0 0 2 8 83h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for modulation and recalled from table 04h at the adjusted memor y address found in tindex. this register is updated at the end of the temperature conversion. table 02h, register 82h?3h: modulation register downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 62 ______________________________________________________________________________________ table 02h, register 84h?5h: dac1 value factory default 0000h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access (pw2 and dac1 en = 0) or (pw1 and rwtbl246 and dac1 e n = 0) memory type volatile 84h 0 0 0 0 0 0 0 2 8 85h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for dac1 and recalled from table 07h at the adjusted memory addr ess found in tindex. this register is updated at the end of the temperature conversion. v dac1 = refin 512 dac1 value factory default 0000h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access (pw2 and dac2 en = 0) or (pw1 and rwtbl246 and dac2 e n = 0) memory type volatile 86h 0 0 0 0 0 0 0 2 8 87h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for dac2 and recalled from table 08h at the adjusted memory add ress found in tindex. this register is updated at the end of the temperature conversion. v dac2 = refin 512 dac2 value table 02h, register 86h?7h: dac2 value downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 63 table 02h, register 88h: sample rate factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) 88h see see see see see apc_sr 2 apc_sr 1 apc_sr 0 bit 7 bit 0 bits 7:3 see bits 2:0 apc_sr[2:0]: 3-bit sample rate for comparison of apc control. defines the sample rate for comparison of apc control. apc_sr[2:0] sample period (t rep ) (ns) 000b 800 001b 1200 010b 1600 011b 2000 100b 2800 101b 3200 110b 4400 111b 6400 downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 64 ______________________________________________________________________________________ factory default 80h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) 89h losc vcctxf inv los asel mask invrsout rselpin invtxf bit 7 bit 0 bit 7 losc: los configuration. defines the source for the losout pin (see figure 16) . 0 = los lo alarm is used as the source. 1 = (default) los input pin is used as the source. bit 6 vcctxf: 0 = vcc lo alarm is not masked on power-up. txfout is high on power -on. 1 = vcc lo alarm is masked on power-on. txfout is low as soon as v cc > v pod . bit 5 inv los: inverts the buffered input pin los or los lo alarm to output pin losout (see fig ure 16). 0 = non in verted los or los lo alarm to losout pin. 1 = inverted los or los lo alarm to losout pin. bit 4 asel: address select. 0 = device address is a2h. 1 = byte device address in table 02h, register 8ch is used as the devic e address. bit 3 mask: 0 = alarm-enable row exists at table 01h, registers f8hCffh. table 0 5h, registers f8hCffh are empty. 1 = alarm-enable row exists at table 05h, registers f8hCffh. table 0 1h, registers f8hCffh are empty. bit 2 invrsout: allow for inversion of rselout pin (see figure 16). 0 = rselout is not inverted. 1 = rselout is inverted. bit 1 rselpin: 0 = bit 6 of the rxctrl1 register written to the max3945 is programmed b y the user. 1 = bit 6 of the rxctrl1 register is determined by the rselout pin polar ity. bit 0 invtxf: allow for inversion of signal driven by the txf input pin. 0 = (default) txf signal is not inverted. 1 = txf signal is inverted. table 02h, register 89h: cnfga downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 65 table 02h, register 8ah: cnfgb factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) 8ah reserved reserved txf_txden reserved reserved alatch qtla tch wlatch bit 7 bit 0 bits 7:6 reserved bit 5 txf_txden: 0 = txfout does not go high when txd goes high. 1 = txfout goes high when txd goes high. bits 4:3 reserved bit 2 alatch: adc alarms comparison latch. lower memory, registers 70hC71h. 0 = adc alarm flags reflect the status of the last comparison. 1 = adc alarm flags remain set. bit 1 qtlatch: quick trips comparison latch. lower memory, registers 72hC73h. 0 = qt alarm flags reflect the status of the last comparison. 1 = qt alarm flags remain set. bit 0 wlatch: adc warnings comparison latch. lower memory, registers 74hC75h. 0 = adc warning flags reflect the status of the last comparison. 1 = adc warning flags remain set. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 66 ______________________________________________________________________________________ table 02h, register 8bh: cnfgc factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) 8bh xoveren invmon2 txdm34 txdfg txdflt txdio rssi_fc rssi_ff bit 7 bit 0 bit 7 xoveren: enables rssi conversion to use the xover (table 02h, register 90hC91h) valu e during mon3 conversions. 0 = uses hysteresis for linear rssi measurements. 1 = xover value is enabled for nonlinear rssi measurements. bit 6 invmon2: 0 = mon2 is referenced to gnd. 1 = mon2 is referenced to v cc . bit 5 txdm34: enables txd to reset alarms and warnings associated to mon3 and mon4 during a txd event. 0 = txd event has no effect on the mon3 and mon4 alarms, warnings, and qu ick trips. 1 = mon3 and mon4 alarms, warnings, and quick trips are reset during a t xd event. bit 4 txdfg: see figure 15. 0 = fetg, an internal signal, has no effect on txdout. 1 = fetg is enabled and ored with other possible signals to create txdout. bit 3 txdflt: see figure 15. 0 = txf pin has no effect on txdout. 1 = txf pin is enabled and ored with other possible signals to cr eate txdout. bit 2 txdio: see figure 15. 0 = (default) txd input signal is enabled and ored with other possi ble signals to create txdout. 1 = txd input signal has no effect on txdout. bits 1:0 rssi_fc and rssi_ff: rssi force coarse and rssi force fine. control bits for rssi mode of operation on the mon3 conversion. 00b = normal rssi mode of operation (default). 01b = the fine settings of scale and offset are used for mon3 conversion s. 10b = the coarse settings of scale and offset are used for mon3 convers ions. 11b = normal rssi mode of operation. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 67 table 02h, register 8dh: reserved factory default 00h read access n/a write access n/a memory type nonvolatile (see) this register is reserved. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) 8eh reserved mon1 2 mon1 1 mon1 0 reserved mon2 2 mon2 1 mon2 0 bit 7 bit 0 allows for right-shifting the final answer of mon1 and mon2 voltage measurement s. this allows for scaling the measurements to the smallest full-scale voltage and then right-shifti ng the final result so the reading is weighted to the correct lsb. table 02h, register 8eh: right-shift 1 (rshift 1 ) factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) 8ch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 this value becomes the i 2 c slave address for the main memory when the asel (table 02h, register 89h) bit i s set. if a0h is programmed to this register, the auxiliary memo ry is disabled. table 02h, register 8ch: device address downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 68 ______________________________________________________________________________________ factory default 30h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) 8fh reserved mon3c 2 mon3c 1 mon3c 0 reserved mon3f 2 mon3f 1 mon3f 0 bit 7 bit 0 allows for right-shifting the final answer of mon3 coarse (mon3c) and mon3 fine (m on3f) voltage measurements. this allows for scaling the measurements to the smallest full-scale v oltage and then right-shifting the final result so the reading is weighted to the correct lsb. table 02h, register 8fh: right-shift 0 (rshift 0 ) table 02h, register 90h?1h: xover coarse factory default 0000h read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) 90h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 91h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 0 bit 7 bit 0 defines the crossover value for rssi measurements of nonlinear inputs when xoveren is set to 1 (table 02h, register 8bh). mon3 coarse conversion results (before right-shifting) less than this registe r are clamped to the value of this register. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 69 factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) these registers are reserved. factory calibrated read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) 92h, 94h, 96h, 98h, 9ah, 9ch 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 93h, 95h, 97h, 99h, 9bh, 9dh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 controls the scaling or gain of the fs voltage measurements. the factory- calibrated value produces an fs voltage of 6.5536v for v cc ; 2.5v for mon1, mon2, mon4; and 0.3125v for mon3 fine. table 02h, register 92h?3h: v cc scale table 02h, register 94h?5h: mon1 scaletable 02h, register 96h?7h: mon2 scale table 02h, register 98h?9h: mon3 fine scale table 02h, register 9ah?bh: mon4 scale table 02h, register 9ch?dh: mon3 coarse scale table 02h, register 9eh?fh: reserved downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 70 ______________________________________________________________________________________ factory default ffffh read access pw2 or (pw1 and rwtbl2) or (pw1 and rtbl2) write access pw2 or (pw1 and rwtbl2) memory type nonvolatile (see) a0h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 a1h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 0 bit 7 bit 0 defines the crossover value for rssi measurements of nonlinear inputs when xoveren is set to 1 (table 02h, register 8bh). mon3 fine conversion results (before right-shifting) greater tha n this register require a mon3 coarse conversion. table 02h, register a0h?1h: xover fine table 02h, register a2h?3h: v cc offset table 02h, register a4h?5h: mon1 offsettable 02h, register a6h?7h: mon2 offset table 02h, register a8h?9h: mon3 fine offset table 02h, register aah?bh: mon4 offset table 02h, register ach?dh: mon3 coarse offset factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) a2h, a4h, a6h, a8h, aah, ach s s 2 15 2 14 2 13 2 12 2 11 2 10 a3h, a5h, a7h, a9h, abh, adh 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 bit 7 bit 0 allows for offset control of these voltage measurements if de sired. this number is twos complement. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 71 factory calibrated read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) aeh s 2 8 2 7 2 6 2 5 2 4 2 3 2 2 afh 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 bit 7 bit 0 allows for offset control of temperature measurement if desired. the final result must be xored with bb40h before writing to this register. factory calibration contains the desire d value for a reading in degrees celsius. table 02h, register aeh?fh: internal temp offset downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 72 ______________________________________________________________________________________ table 02h, register b0h?3h: pw1 factory default ffff ffffh read access n/a write access pw2 or (pw1 and wpw1) memory type nonvolatile (see) b0h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 b1h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 b2h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 b3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the pwe value is compared against the value written to this locat ion to enable pw1 access. at power-on, the pwe value is set to all ones. thus, writing these bytes to all ones gr ants pw1 access on power-on without writing the password entry. all reads of this register are 00h. factory default ffff ffffh read access n/a write access pw2 memory type nonvolatile (see) b4h 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 b5h 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 b6h 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 b7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the pwe value is compared against the value written to this locatio n to enable pw2 access. at power-on, the pwe value is set to all ones. thus, writing these bytes to all ones gr ants pw2 access on power-on without writing the password entry. all reads of this register are 00h. table 02h, register b4h?7h: pw2 downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 73 table 02h, register b8h: los ranging factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) b8h reserved hlos 2 hlos 1 hlos 0 reserved llos 2 llos 2 1 llos 0 bit 7 bit 0 this register controls the full-scale range of the quick-trip monito ring for the differential inputs of mon3. bit 7 reserved (default = 0) bits 6:4 hlos[2:0]: hlos fll-scale ranging. 3-bit value to select the fs comparison voltage for high los found on mon3. default is 000b and creates an fs of 1.25v. hlos[2:0] % of 1.25v fs voltage (v) 000b 100.00 1.250 001b 80.00 1.000 010b 66.67 0.833 011b 50.00 0.625 100b 40.00 0.500 101b 33.33 0.417 110b 28.57 0.357 111b 25.00 0.313 bit 3 reserved (default = 0) bits 2:0 llos[2:0]: llos fll-scale ranging. 3-bit value to select the fs comparison voltage for low los found on mon3. default is 000b and creates an fs of 1.25v. llos[2:0] % of 1.25v fs voltage (v) 000b 100.00 1.250 001b 80.00 1.000 010b 66.67 0.833 011b 50.00 0.625 100b 40.00 0.500 101b 33.33 0.417 110b 28.57 0.357 111b 25.00 0.313 downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 74 ______________________________________________________________________________________ table 02h, register b9h: comp ranging factory default 00h read access pw2 write access pw2 memory type nonvolatile (see) b9h reserved bias 2 bias 1 bias 0 reserved apc 2 apc 1 apc 0 bit 7 bit 0 the upper nibble of this byte controls the full-scale range of the quick-trip mon itoring for bias. the lower nibble of this byte controls the full-scale range for the quick-trip monitoring of the apc reference as well as the closed-loop monitoring of apc. bit 7 reserved (default = 0) bits 6:4 bias[2:0]: bias fll-scale ranging. 3-bit value to select the fs comparison voltage for bias found on mon1. default is 000b and creates an fs of 1.25v. bias[2:0] % of 1.25v fs voltage (v) 000b 100.00 1.250 001b 80.00 1.000 010b 66.67 0.833 011b 50.00 0.625 100b 40.00 0.500 101b 33.33 0.417 110b 28.57 0.357 111b 25.00 0.313 bit 3 reserved (default = 0) bits 2:0 apc[2:0]: apc fll-scale ranging. 3-bit value to select the fs comparison voltage for mon2 with the apc. default is 000b and creates an fs of 2.5v. apc[2:0] % of 2.50v fs voltage (v) 000b 100.00 2.500 001b 80.00 2.000 010b 66.67 1.667 011b 50.00 1.250 100b 40.00 1.000 101b 33.33 0.833 110b 28.57 0.714 111b 25.00 0.625 downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 75 table 02h, register bah: isteph factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) bah 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 bit 7 bit 0 istep is the initial step value used at power-on or after a txd pulse to co ntrol the bias register. the particular istep used depends on the value of tindex and istepti (table 02h, regi ster c5h). when tindex > istepti, isteph is used. when tindex < istepti, istepl is used. at startup, this value plu s 2 0 = 1 is continuously added to the bias register value until the apc feedback (mon2) is greater than its threshold. at that time, a binary search is used to complete the startup of the apc closed loop. if the resul ting math operation is greater than ibiasmax (table 02h, register eeh), the result is not loaded into th e bias register, but the binary search is begun to complete the initial search for apc. during startup, the bias regi ster steps causing a higher bias value than ibiasmax do not create the bias max alarm. the bias max alarm detection i s enabled at the end of the binary search. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) bbh 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 bit 7 bit 0 see the isteph register description. table 02h, register bbh: istepl downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 76 ______________________________________________________________________________________ factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) bch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 fast-comparison dac threshold adjust for high txp. this value is add ed to the apc dac value recalled from table 06h. if the sum is greater than 0xff, 0xff is used. comparisons greater than v htxp , compared against v mon2 , create a txp hi alarm. the same ranging applied to the apc dac should be us ed here. v htxp = full scale 255 htxp + apc dac () table 02h, register bch: htxp table 02h, register bdh: ltxp factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) bdh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 fast-comparison dac threshold adjust for low txp. this value is subtracte d from the apc dac value recalled from table 06h. if the difference is less than 0x00, 0x00 is used. comp arisons less than v ltxp , compared against v mon2 , create a txp lo alarm. the same ranging applied to the apc dac shoul d be used here. v ltxp = full scale 255 apc dac ltxp () downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 77 factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) beh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 fast-comparison dac threshold adjust for high los. the combination of hlos and llos creates a hysteresis comparator. as rssi falls below the llos threshold, the los lo alarm bit is s et to 1. the los alarm remains set until the rssi input is found above the hlos threshold setting, which c lears the los lo alarm bit and sets the los hi alarm bit. at power-on, both los lo and los hi alarm bits are 0 and the hysteresis comparator uses the llos threshold setting. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) bfh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 fast-comparison dac threshold adjust for low los. see hlos (table 02h, register beh) for functi onal description. table 02h, register beh: hlostable 02h, register bfh: llos downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 78 ______________________________________________________________________________________ table 02h, register c0h: pw_ena factory default 10h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) c0h rwtbl78 rwtbl1c rwtbl2 rwtbl1a rwtbl1b wlower wauxa wauxb bit 7 bit 0 bit 7 rwtbl78: tables 07hC08h 0 = (default) read and write access for pw2 only. 1 = read and write access for both pw1 and pw2. bit 6 rwtbl1c: table 01h or 05h bytes f8hCffh. table address is dependent on mask bit (table 02 h, register 89h). 0 = (default) read and write access for pw2 only. 1 = read and write access for both pw1 and pw2. bit 5 rwtbl2: tables 02h, except for pw1 value locations (table 02h, registers b0hCb 3h). 0 = (default) read and write access for pw2 only. 1 = read and write access for both pw1 and pw2. bit 4 rwtbl1a: read and write table 01h, registers 80hCbfh 0 = read and write access for pw2 only. 1 = (default) read and write access for both pw1 and pw2. bit 3 rwtbl1b: read and write table 01h, registers c0hCf7h 0 = (default) read and write access for pw2 only. 1 = read and write access for both pw1 and pw2. bit 2 wlower: write lower memory bytes 00hC5fh in main memory. all users can read this a rea. 0 = (default) write access for pw2 only. 1 = write access for both pw1 and pw2. bit 1 wauxa: write auxiliary memory, registers 00hC7fh. all users can read this area. also see table 02h, register c1h, pw_enb. 0 = (default) write access for pw2 only. 1 = write access for both pw1 and pw2. bit 0 wauxb: write auxiliary memory, registers 80hCffh. all users can read this area. also see table 02h, register c1h, pw_enb. 0 = (default) write access for pw2 only. 1 = write access for both pw1 and pw2. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 79 table 02h, register c1h: pw_enb factory default 03h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) c1h rwtbl46 rtbl1c rtbl2 rtbl1a rtbl1b wpw1 wauxau wauxbu bit 7 bit 0 bit 7 rwtbl46: read and write tables 04h, 06h 0 = (default) read and write access for pw2 only. 1 = read and write access for both pw1 and pw2. bit 6 rtbl1c: read table 01h or table 05h, registers f8hCffh. table address is dependent on mask bit (table 02h, register 89h). 0 = (default) read access for pw2 only. 1 = read access for pw1 and pw2. bit 5 rtbl2: read table 02h except for pw1 value locations (table 02h, registers b0hC b3h) 0 = (default) read access for pw2 only. 1 = read access for pw1 and pw2. bit 4 rtbl1a: read table 01h, registers 80hCbfh 0 = (default) read access for pw2 only. 1 = read access for pw1 and pw2. bit 3 rtbl1b: read table 01h, registers c0hCf7h 0 = (default) read access for pw2 only. 1 = read access for pw1 and pw2. bit 2 wpw1: write register pw1 (table 02h, registers b0hCb3h). for security pu rposes these registers are not readable. 0 = (default) write access for pw2 only. 1 = write access for pw1 and pw2. bit 1 wauxau: write auxiliary memory, registers 00hC7fh. all users can read this area. also see table 02h, register c0h, pw_ena. 0 = write access for pw2 only. 1 = (default) write access for user, pw1 and pw2. bit 0 wauxbu: write auxiliary memory, registers 80hCffh. all users can read this area. also see table 02h, register c0h, pw_ena. 0 = read and write access for pw2 only. 1 = (default) read and write access for user, pw1 and pw2. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 80 ______________________________________________________________________________________ table 02h, register c2h: modti factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) c2h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the modulation temperature index defines the tempco boundary for the modulation lut. the modtc bit (table 02h, register c6h) defines the polarity of the tempco. modti = temp _ value + 40 c 2 c + 80h factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) c3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 dac1 temperature index (dac1ti) defines the tempco boundary for the dac1 lut. the dac1tc b it (table 02h, register c6h) defines the polarity of the tempco. this value is compared with t he adjusted memory address used during the lut recall, not the value in the tindex register (table 0 2h, register 81h). dac1ti = temp _ value + 40 c 4 c + 80h table 02h, register c3h: dac1ti downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 81 table 02h, register c4h: dac2ti factory default 00h read access pw2 or (pw1 and rwtbl 246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl 246) memory type nonvolatile (see) c4h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 dac2 temperature index defines the tempco boundary for the dac2 lut. the dac2tc bit (table 02h, regist er c6h) defines the polarity of the tempco. this value is compared with the adjusted memory address u sed during the lut recall, not the value in the tindex register (table 02h, register 81h). dac2ti = temp _ value + 40 c 4 c + 80h factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) determines which value between isteph and istepl is used as the istep. tindex > is tepi, isteph is used. tindex < istepti, istepl is used. table 02h, register c5h: istepti downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 82 ______________________________________________________________________________________ table 02h, register c6h: luttc factory default 00h read access pw2 or (pw1 and rwtbl 246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl 246) memory type nonvolatile (see) c6h modtc dac1tc dac2tc reserved reserved reserved reserved reserved bit 7 bit 0 bit 7 modtc: modulation tempco 0 = positive tempco. for a tindex (table 02h, register 81h) below the modti value (table 02h, register c2h), the 8-bit recalled value from the modulation lut is stored in the lower 8 b its of the modulation register. for a tindex greater than or equal to modti, the recalled value is stored in the upper 8 bits of the modulation register. 1 = negative tempco. for a tindex below the modti value, the 8-bit recalled value from the modulation lut is stored in the upper 8 bits of the modulation register. for a tindex greater than or equal to modti, the recalled value is stored in the lower 8 bits of the modulation re gister. bit 6 dac1tc: dac1 tempco 0 = positive tempco. for a tindex (table 02h, register 81h) below the dac1ti value (table 02h, register c3h), the 8-bit recalled value from the dac1 lut is stored in the lowe r 8 bits of the dac1 dacs register. for a tindex greater than or equal to dac1ti, the recalled value is stored i n the upper 8 bits of the dac1 dacs register. 1 = negative tempco. for a tindex below the dac1ti value, the 8-bit recalled value from the dac1 lut is stored in the upper 8 bits of the dac1 dacs register. for a tindex greater than or equal to dac1ti, the recalled value is stored in the lower 8 bits of the dac1 dacs regis ter. bit 5 dac2tc: dac2 tempco 0 = positive tempco. for a tindex (table 02h, register 81h) below the dac2ti value (table 02h, register c4h), the 8-bit recalled value from the dac2 lut is stored in the lowe r 8 bits of the dac2 dacs register. for a tindex greater than or equal to dac2ti, the recalled value is stored i n the upper 8 bits of the dac2 dacs register. 1 = negative tempco. for a tindex below the dac2ti value, the 8-bit recalled value from the dac2 lut is stored in the upper 8 bits of the dac2 dacs register. for a tindex greater than or equal to dac2ti, the recalled value is stored in the lower 8 bits of the dac2 dacs regis ter. bits 4:0 reserved downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 83 table 02h, register c7h: tblselpon factory default 00h read access pw2 or (pw1 and rwtbl 246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl 246) memory type nonvolatile (see) c7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 chooses the initial value for the table-select byte (lower memory, register 7fh) at power-on. factory default 0000h read access pw2 or (pw1 and rwtbl 246) or (pw1 and rtbl246) write access (pw2 and bias en = 0) or (pw1 and rwtb l246 and bias en = 0) memory type volatile c8h 0 0 0 0 0 0 0 2 8 c9h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 when bias en (table 02h, register 80h) is written to 0, writes to these bytes control the bias register , which then updates a maxim laser driver set_ibias register. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access (pw2 and bias en = 0) or (pw1 and rwtbl246 and bias en = 0) memory type volatile cah reserved reserved reserved reserved reserved reserved reserved man_clk bit 7 bit 0 when bias en (table 02h, register 80h) is written to 0, man_clk controls the updates of the man bias va lue to the bias register. this new value is sent through the 3-wire interface. the values of man bias must be wri tten with a separate write command. setting man_clk to a 1 clocks the man bias value to the bias register, which then updates a maxim laser driver set_ibias register. 1) write the man bias value with a write command. 2) set the man_clk bit to a 1 with a separate write command. 3) clear the man_clk bit to a 0 with a separate write command. table 02h, register c8h?9h: man biastable 02h, register cah: man_cntl downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 84 ______________________________________________________________________________________ table 02h, register cbh?ch: bias register factory default 0000h read access pw2 or (pw1 and rwtbl 246) or (pw1 and rtbl246) write access n/a memory type volatile cbh reserved reserved reserved reserved reserved reserved reserved 2 8 cch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for bias and resolved from the apc. this register is updated after each decision of the a pc loop. factory default 00h read access pw2 or (pw1 and rwtbl 246) or (pw1 and rtbl246) write access (pw2 and apc en = 0) or (pw1 and rwtbl 246 and apc en = 0) memory type volatile cdh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value used for apc reference and recalled from table 06h at the adjusted memory address found in tindex. this register is updated at the end of the temperature conversion. factory default 78h read access pw2 or (pw1 and rwtbl 246) or (pw1 and rtbl246) write access n/a memory type rom ceh 0 1 1 1 1 0 0 0 bit 7 bit 0 hardwired connections to show the device id. table 02h, register cdh: apc dactable 02h, register ceh: device id downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 85 table 02h, register cfh: device ver factory default device version read access pw2 or (pw1 and rwtbl 246) or (pw1 and rtbl246) write access n/a memory type rom cfh device version bit 7 bit 0 hardwired connections to show the device version. factory default 00h read access pw2 or (pw1 and rwtbl 246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl 246) memory type nonvolatile (see) d0hCd7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 high-bias alarm threshold (hbath) is a digital clamp used to ensure that the dac setting for bias currents does not exceed a set value. the table below shows the range of temperature for each bytes location. the table shows a rising temperature; for a falling temperature there is 1c of hysteresis. d0h less than or equal to -8c d1h greater than -8c up to +8c d2h greater than +8c up to +24c d3h greater than +24c up to +40c d4h greater than +40c up to +56c d5h greater than +56c up to +72c d6h greater than +72c up to +88c d7h greater than +88c table 02h, register d0h?7h: hbath downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 86 ______________________________________________________________________________________ table 02h, register e8h: rxctrl1 factory default 00h read access n/a write access n/a memory type n one these registers do not exist. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) e8h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), the maxim laser driver tx_por bit is set high (visible in 3w txstat1, bit 7), or on a rising edge of txd, this va lue is written to a maxim laser driver through the 3-wire interface. see the in1, rsel, rselout section for additional details. factory default 00h read access pw2 or (pw1 and rwtbl 246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl 246) memory type nonvolatile (see) e9h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), the maxim laser driver tx_por bit is set high (visible in 3w txstat1, bit 7), or on a rising edge of txd, this value is written to a max im laser driver through the 3-wire interface. table 02h, register d8h?7h: emptytable 02h, register e9h: rxctrl2 downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 87 table 02h, register eah: setcml factory default 00h read access pw2 or (pw1 and rwtbl 246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl 246) memory type nonvolatile (see) eah 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), the maxim laser driver tx_por bit is set high (visible in 3w txstat1, bit 7), or on a rising edge of txd, this value is written to a maxi m laser driver through the 3-wire interface. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) ebh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. only written if setlosctl is 1. if setlosctl is 0, the setlosl register is used. after either v cc exceeds poa (after a por event), the maxim laser driver tx_por bit is set high (visible in 3w txstat1, bit 7), or on a rising edge of txd, this value is written to a m axim laser driver through the 3-wire interface. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) ech 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), the maxim laser driver tx_por bit is set high (visible in 3w txstat1, bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. table 02h, register ebh: setloshtable 02h, register ech: txctrl downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 88 ______________________________________________________________________________________ table 02h, register edh: imodmax factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) edh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), the maxim laser driver tx_por bit is se t high (visible in 3w txstat1, bit 7), or on a rising edge of txd, this value i s written to a maxim laser driver through the 3-wire interface. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) eeh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), the maxim laser driver tx_por bit is set high (visible in 3w txstat1, bit 7) or on a rising edge of txd, this va lue is written to a maxim laser driver through the 3-wire interface. in addition, this value defines the maximum dac value allowed for the upper 8 bits of bias output during apc closed-loop operations. during the intial step and bi nary search, this value does not cause an alarm but still clamps the bias register value. after the startup seqence (or normal apc operations), if the apc loop tries to create a bias value greater than this setting, it is c lamped and creates a max bias alarm. table 02h, register eeh: ibiasmax downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 89 table 02h, register efh: setpwctrl factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) efh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), the maxim laser driver tx_por bit is set high (visible in 3w txstat1, bit 7), or on a rising edge of txd, this va lue is written to a maxim laser driver through the 3-wire interface. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) f0h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. after either v cc exceeds poa (after a por event), the maxim laser driver tx_por bit is set high (visible in 3w txstat1, bit 7), or on a rising edge of txd, this va lue is written to a maxim laser driver through the 3-wire interface. table 02h, register f0h: settxde downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 90 ______________________________________________________________________________________ table 02h, register f2h: setlostimer factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) f1h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. the writing of this register is enabled using exctrl[1:0]. after either v cc exceeds poa (after a por event), the maxim laser driver tx_por bit is set high (vis ible in 3w txstat1, bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) f2h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. the writing of this register is enabled using exctrl[1:0]. after either v cc exceeds poa (after a por event), the maxim laser driver tx_por bit is set high (vis ible in 3w txstat1, bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. table 02h, register f1h: settxeq downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 91 table 02h, register f3h: setlosl factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) f3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. only written if setlosctl is 0. if setlos ctl is 1, then setlosh register is used. after either v cc exceeds poa (after a por event), the maxim laser driver tx_por bit is set high (visible in 3w txstat1, bit 7), or on a rising edge of txd, this value is written to a maxim la ser driver through the 3-wire interface. table 02h, register f4h: rxctrl3 factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) f4h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. the writing of this register is enabled using exctrl[1:0]. after either v cc exceeds poa (after a por event), the maxim laser driver tx_por bit is set high (vis ible in 3w txstat1, bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 92 ______________________________________________________________________________________ table 02h, register f5h: txctrl2 factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) f5h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. the writing of this register is enabled using exctrl[1:0]. after either v cc exceeds poa (after a por event), the maxim laser driver tx_por bit is set high (vis ible in 3w txstat1, bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. table 02h, register f6h: txctrl3 factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) f6h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. the writing of this register is enabled using exctrl[1:0]. after either v cc exceeds poa (after a por event), the maxim laser driver tx_por bit is set high (vis ible in 3w txstat1, bit 7), or on a rising edge of txd, this value is written to a maxim laser driver through the 3-wire interface. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 93 table 02h, register f7h: 3wset factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) f7h reserved reserved reserved reserved reserved txpordis exctrl1 exctrl2 bit 7 bit 0 bits 7:3 reserved bit 2 txpordis: transmit por disable. 0 = the 3-wire interface monitors the txpor bit in the laser drivers txstat1 register. 1 = the 3-wire interface ignores the txpor bit in the laser drivers txstat1 r egister. bits 1:0 exctrl[1:0]: extra 3-wire control register selection. used to enable/disable th e 3-wire registers. 00 = settxeq and setlostimer are enabled. 01 = device mode. settexeq, setlostimer, rxctrl3, txctrl2, and txc trl3 are disabled. 10 = settxeq, setlostimer, and rxctrl3 are enabled. 11 = settxeq, setlostimer, rxctrl3, txctrl2, and txctrl3 are enabled. table 02h, register f8h: 3wctrl factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type volatile f8h reserved reserved reserved reserved reserved reserved 3wrw 3wdi s bit 7 bit 0 bits 7:2 reserved bit 1 3wrw: initiates a 3-wire write or read operation. the write command uses the memor y address found in the 3-wire address register (table 02h, register f9h) and the data from the 3-wire write register (table 02h, register fah). this bit clears itself at the completi on of the write operation. the read command uses the memory address found in the 3-wire address register (tabl e 02h, register f9h). the address determines whether a read or write operation is to be perfor med. this bit clears itself at the completion of the read operation. 0 = (default) reads back as 0 when the write or read operation is compl eted. 1 = initiates a 3-wire write or read operation. bit 0 3wdis: disables all automatic communication across the 3-wire interface. this include s all updates from the luts, apc loop, and status registers. the only 3-wire com munication is with the manual mode of operation. 0 = (default) automatic communication is enabled. 1 = disables automatic communication. downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 94 ______________________________________________________________________________________ table 02h, register fah: write factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) fah 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 this byte is used during manual 3-wire communication. when a manual writ e is initiated, this register contains the data for the operation. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (see) f9h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 this byte is used during manual 3-wire communication. when a manual read or write is initiated, this register contains the address for the operation. table 02h, register f9h: address downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 95 factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access n/a memory type volatile fbh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 this byte is used during maunual 3-wire communication. when a manual read is initiated, the return data is stored in this register. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access n/a memory type nonvolatile (see) fch 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. this value is read from the maxim laser driver wi th the 3-wire interface every t rr (see the maxim laser drivers electrical characteristics). table 02h, register fbh: readtable 02h, register fch: txstat1 table 02h, register fdh: txstat2 factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access n/a memory type nonvolatile (see) fdh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 a 3-wire slave register. this value is read from the maxim laser driver wi th the 3-wire interface every t rr (see the maxim laser drivers electrical characteristics). downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 96 ______________________________________________________________________________________ factory default 00h read access n/a write access n/a memory type nonvolatile (see) these registers are reserved. factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (ee) 80hCc7h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the digital value for the modulation dac output. the modulation lut is a set of registers assigned to hold the temperature profile for the modulation register. the temperature measurement is used to index the lut (tindex, table 02h, register 81h) in 2c increments from - 40c to +102c, starting at 80h. register 80h defines the -40c to -38c mod output, register 81h defines the -38c to -36c mod output, a nd so on. values recalled from this eeprom memory table are written into the modulation register (table 02h, register 82hC83h) location that holds the value until the next temperature conversion. the de vice can be placed into a manual mode (mod en bit, table 02h, register 80h), where the modulat ion register is directly controlled for calibration. if the temperature compensation functionality is not required, then program the entire table 04h to the desired modulation setting. the modtc bit determines whether the 8-bit lut v alues are loaded into the upper 8 bits or lower 8 bits of the 9-bit mod dac. see the bias and modulation control during poer-up section for more information. table 02h, register feh?fh: reserved table 04h register description table 04h, register 80h?7h: modulation lut downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 97 table 06h register descriptions table 06h, register 80h?3h: apc lut factory default 00h read access pw2 or (pw1 and rwtbl246) or (pw1 and rtbl246) write access pw2 or (pw1 and rwtbl246) memory type nonvolatile (ee) 80hCa3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the apc lut is a set of registers assigned to hold the temperature profile for the apc reference dac. the values in this table combined with the apc bits in the comp ranging register (table 02h, register b9h) determine the set point for the apc loop. the temperature measurement is used to inde x the lut (tindex, table 02h, register 81h) in 4c increments from -40c to +100c, starting at register 80h. reg ister 80h defines the -40c to -36c apc reference value, register 81h defines the -36c to -32c apc reference v alue, and so on. values recalled from this eeprom memory table are written into the apc dac (tabl e 02h, register cdh) location that holds the value until the next temperature conversion. the device can be placed into a manual mode (apc en bit, table 02h, register 80h), where the apc dac can be directly c ontrolled for calibration. if te temperature compensation is not required by the application, program the entire lut t o the desired apc set point. factory default 00h read access n/a write access n/a memory type nonvolatile (ee) these registers are reserved. table 06h, register a4h?7h: reserved downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 98 ______________________________________________________________________________________ table 07h register descriptions table 07h, register 80h?3h: dac1 lut factory default 00h read access pw2 or (pw1 and rwtbl78) and (pw1 and rtbl78) write access pw2 or (pw1 and rwtbl78) memory type nonvolatile (ee) 80hCa3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the dac1 lut is a set of registers assigned to hold the pwm profile for dac1. t he values in this table determine the set point for dac1. the temperature measurement is used to index the lut (tinde x, table 02h, register 81h) in 4c increments from -40c to +100c, starting at register 80h. regis ter 80h defines the -40c to -36c dac1 value, register 81h defines -36c to -32c dac1 value, and so on. value s recalled from this eeprom memory table are written into the dac1 value (table 02h, reg isters 84hC85h) location, which holds the value until the next temperature conversion. the part can be placed into a man ual mode (dac1 en bit, table 02h, register 80h), where dac1 can be directly controlled for calibration. if temperature co mpensation is not required by the application, program the entire lut to the desired dac1 set point. the dac1tc bit determines whether the 8-bit lut values are loaded into the upper 8 bits or lower 8 bits of th e 9-bit dac1. see the delta- sigma outputs (dac1 and dac2) section for more information. factory default 00h read access pw2 or (pw1 and rwtbl78) or (pw1 and rtbl78) write access pw2 or (pw1 and rwtbl78) memory type nonvolatile (ee) these registers are reserved. table 07h, register a4h?7h: reserved downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface ______________________________________________________________________________________ 99 table 08h register descriptions table 08h, register 80h?3h: dac2 lut factory default 00h read access pw2 or (pw1 and rwtbl78) or (pw1 and rtbl78) write access pw2 or (pw1 and rwtbl78) memory type nonvolatile (ee) 80hCa3h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 the dac2 lut is set of registers assigned to hold the pwm profile for dac2. the values in this table determine the set point for dac2. the temperature measurement is used to index the lut (tindex , table 02h, register 81h) in 4c increments from -40c to +100c, starting at register 80h. regis ter 80h defines the -40c to -36c dac2 value, register 81h defines -36c to -32c dac2 value, and so on. values r ecalled from this eeprom memory table are written into the dac2 value (table 02h, registers 86hC87h) locat ion that holds the value until the next temperature conversion. the device can be placed into a manual mo de (dac2 en bit, table 02h, register 80h), where dac2 can be directly controlled for calibration. if temperature compensa tion is not required by the application, program the entire lut to the desired dac2 set point. the da c2tc bit determines whether the 8-bit lut values are loaded into the upper 8 bits or lower 8 bits of the 9-bit d ac2. see the delta-sigma outputs (dac1 and dac2) section for more information. factory default 00h read access n/a write access n/a memory type nonvolatile (ee) these registers are reserved. table 08h, register a4h?7h: reserved downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface 100 _____________________________________________________________________________________ applications information power-supply decoupling to achieve best results, it is recommended that the powersupply is decoupled with a 0.01? or a 0.1? capacitor. use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the v cc and gnd pins to minimize lead inductance. sda and scl pullup resistors sda is an open-collector output on the device thatrequires a pullup resistor to realize high logic levels. a master using either an open-collector output with a pullup resistor or a push-pull output driver can be uti- lized for scl. pullup resistor values should be chosen to ensure that the rise and fall times listed in the i 2 c ac electrical characteristics table are within specification. package information for the latest package outline information and land patterns,go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. packagedrawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. factory default 00h read access pw2 or (pw1 and wauxa) or (pw1 and wauxau) write access pw2 or (pw1 and wauxa) memory type nonvolatile (ee) 00hCffh 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 accessible with the slave address a0h. auxiliary memory a0h register description auxiliary memory a0h, register 00h?fh: eeprom package type package code outline no. land pattern no. 28 tqfn-ep t2855+6 21-0140 90-0026 downloaded from: http:///
DS1878 sfp+ controller with digital ldd interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ___________________ 101 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 9/10 initial release 1 8/11 added information about the rselpin bit to the in1, rsel, rselout section and table 02h, register 89: cnfga ; added information about the vcctxf and txf_txden bits to the transmit fault (txfout) output section, table 02h, register 89: cnfga , and table 02h, register 8ah: cnfgb 22C26, 64, 65 downloaded from: http:///

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